Monday, April 8th 2019
AMD "Castle Peak," "Rome," and "Matisse" Referenced in Latest AIDA64 Changelog
FinalWire over the past week posted the latest public beta of AIDA64, which adds support for the three key processor product lines based on AMD's "Zen 2" microarchitecture. The "Matisse" multi-chip module, which received extensive coverage over the past few weeks, will be AMD's main derivative of "Zen 2," designed for the client-segment socket AM4 platform, with up to 16 CPU cores, and the initial flagship product featuring 12 cores. "Rome" is AMD's all-important enterprise-segment MCM for the SP3 platform, with up to 64 CPU cores spread across eight 8-core chiplets interfacing a centralized I/O controller die with a monolithic 8-channel memory controller. It so happens that AMD also wants to update its Ryzen Threadripper line of high-end desktop processors, with "Castle Peak."
"Castle Peak" is codename for 3rd generation Ryzen Threadripper and a client-segment derivative of the "Rome" MCM with a reconfigured I/O controller die that has a monolithic 4-channel DDR4 memory interface, and an unspecified number of CPU cores north of 24. This is for backwards compatibility with the existing AMD X399 motherboards. AMD configures core-count by physically changing the number of 8-core chiplets on the MCM, in addition to disabling cores in groups of 2 within the chiplet. The company could scale core counts looking at its competitive environment. The monolithic quad-channel memory interface could significantly improve the chip's memory performance compared to current-generation Threadrippers, particularly the Threadripper WX series chips in which half the CPU cores are memory bandwidth-starved. The AIDA64 update also improves detection of existing Ryzen/EPYC processors with the K17.3 and K17.5 integrated northbridges.
DOWNLOAD: FinalWire AIDA64 Extreme 5.99.4983 beta
"Castle Peak" is codename for 3rd generation Ryzen Threadripper and a client-segment derivative of the "Rome" MCM with a reconfigured I/O controller die that has a monolithic 4-channel DDR4 memory interface, and an unspecified number of CPU cores north of 24. This is for backwards compatibility with the existing AMD X399 motherboards. AMD configures core-count by physically changing the number of 8-core chiplets on the MCM, in addition to disabling cores in groups of 2 within the chiplet. The company could scale core counts looking at its competitive environment. The monolithic quad-channel memory interface could significantly improve the chip's memory performance compared to current-generation Threadrippers, particularly the Threadripper WX series chips in which half the CPU cores are memory bandwidth-starved. The AIDA64 update also improves detection of existing Ryzen/EPYC processors with the K17.3 and K17.5 integrated northbridges.
DOWNLOAD: FinalWire AIDA64 Extreme 5.99.4983 beta
8 Comments on AMD "Castle Peak," "Rome," and "Matisse" Referenced in Latest AIDA64 Changelog
I have heard rumors that the initial top end will be twelve cores but has there been any confirmation of this?