Wednesday, August 28th 2019
AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit
AMD reached a settlement in the Class Action Lawsuit filed against it, over alleged false-marketing of the core-counts of its eight-core FX-series processors based on the "Bulldozer" microarchitecture. Each member of the Class receives a one-time payout of USD $35 per chip, while the company takes a hit of $12.1 million. The lawsuit dates back to 2015, when Tony Dickey, representing himself in the U.S. District Court for the Northern District of California, accused AMD of false-marketing of its FX-series "Bulldozer" processor of having 8 CPU cores. Over the following four years, the case gained traction as a Class Action was built against AMD this January.
In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
Image Credit: Taylor Alger
Source:
The Register
In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
291 Comments on AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit
The front-end for a monolithic dual-core can be statically partitioned between cores in multi-core fashion(CMP2).
The front-end for a monolithic dual-core can be competitively shared between cores in vertical multithreaded fashion(VMT2).
The front-end for a monolithic dual-core can be algorithmic-priority partitioned between cores in simultaneous multithreaded fashion(SMT2).
The front-end for a monolithic dual-core can be competitively partitioned between cores in clustered multithreaded fashion(CMT2).
Even in VMT just because it fetches/decodes/dispatches for a single core, doesn't mean there aren't two cores. As the FE isn't actually a defining feature of a core, it's an optional feature. They could always skip the front-end and directly interconnect to the cores themselves.
---
Including the FPU, one would have to prove against a similar design that they made a FPU that is only optimized for single-core usage.
Husky per core; 1x 128-bit add + 1x128-bit mul + 1x128-bit fmisc // 84-entry flight window + 42-entry FPU scheduler + 120-entry PRF <== 32-nm node
Bobcat per core; 1x 64-bit add + 1x 64-bit mul // 40-entry flight window + 18-entry FPU scheduler + 88-entry PRF <== 40-nm node
Bulldozer per dual-core; 2x 128-bit Fused-multiply add, 2x 128-bit Packed Integer vALUs // 2*128-entry flight window + 64-entry FPU scheduler + 160-entry PRF <== 32-nm node
Zen per core; 2x128-bit FMUL, 2x128-bit FADD // 192-entry flight window + 36-entry FPU scheduler + 160-entry PRF <== 14-nm node
Clearly, that is not the case.
40nm => 160nm CPP/120nm Mx, 130nm My, and within Intel's 32nm league with density, thus within spitting of GloFo's 32nm.
32nm => 130nm CPP/104nm Mx, two cores Husky and Bulldozer.
14nm => 78nm CPP/64nm Mx, basically two full nodes from 32nm.
"control unit" = "Core IF"
There's only four of those, because there's only four cores.Except your lines are completely wrong on Bulldozer (but right on the 8-core Xeon). You just evidenced that they aren't cores because, as Feng said, "core replication is obvious."
...I'm not even sure that picture is 100% accurate...
AMD settled.
legal-dictionary.thefreedictionary.com/settlementInteger clusters are not cores and the plaintiffs were, in fact, mislead by AMD's claims to the contrary. If AMD tries to create a CMT architecture in the future, this case will be used as precedent to again declare that integer clusters are not cores.
Ohwell, what I have still does what it does. Fx 8350.
On a native octo-core, there eight of them on the die. On AMD's Husky this unit is called the Instruction Control Unit. Even though it is renamed in this image it still is the control unit.
i.e.: a friend has an argument i don't agree and is very stubborn with it, (in that case, that was also about core count on something but i can't remember what it was :p ah yes ... it was on core count of a Pentium 4 HT back in the days ) i tell him "ok ok, you are right, in your own perception, ok i pay you a beer so we can settle this" so he can stop rambling about it and trying to prove his point.
4 dual core module which each core on each modules share the same FPU/Scheduler is, 4x2=8, an octacore (if it was a quadcore ... it wouldn't beat a Intel Equivalent quadcore on certain heavily threaded application and not only by a 2more core margin same for the hexacore FX 6XXX which had 3 dual core modules .)
they paid so it can shut up.
other than that, you are right, wanna grab a beer? :toast:
By contrast, despite the weakness of the individual cores in Bulldozer/Piledriver, 8 of its cores were faster than 6 or 4 or 2 or 1.
Apples and oranges comparison. The 512 MB partition of the 970 was completely unacceptable in its extreme slowness. It was a clear case of fraudulent marketing.
"Half-truths" are not truths. When the performance is as bad as it was for that partition it doesn't qualify in anyone's book for DDR5-class.
pds.ucdenver.edu/document/hardware/AMDbulldozer-IEEE-Computer-2011.pdf
There's also a contradiction in this document in the intro:Those are antonyms.
as i said ... wanna grab a beer? you are right.
additionally ... not everythings ruled by a court is 100% right ...
(This, incidentally, also works in the favor of corporate executives. Insiders on MSNBC, for example, stated — without a hint of concern over the morality of the policy — that the Justice Department has a strong "unofficial" policy of going out of its way to not charge corporate executives with crimes — instead resorting to fines. The argument the insiders presented, which is utterly specious, is that the policy is better for the little people — the workers at the corporations — because, according to the broken logic, fines won't put companies out of business but, somehow, sending executive-class criminals to jail will. This illogic requires the absurd belief that those jobs can't be filled by others. It also ignores the apparent fact that those fines are more likely to come out of the compensation package/jobs of the lower-level workers than they are likely to dent the golden parachutes of the CEOs and such.)
"Fine and forget" is the standard operating procedure for the transfer of wealth into the upper crust these days. It gives the system the illusion of accountability.
There's something about Bulldozer that's unique to its first iteration of design that was never done before it:
Instruction decode is 1:2 instead of 1:1. This proves dependence because without an independent means to decode instructions, the integer clusters cannot operate independently.
AMD proved this was a design flaw because in Steamroller, they decided to not share instruction decode...
...they wouldn't have done that if their original argument was correct. They decided more independency is better, affirming the plaintiffs argument that AMD misrepresented their product.
Jaguar also had design compromises to fill its reduced power consumption and reduced production cost niche. It is hardly a repudiation of Bulldozer/Piledriver either as it has worse IPC than even Bulldozer as far as I know.
Piledriver was the direct replacement for Bulldozer and it was never replaced until Zen 1.
still 8 core on 4x2core module.
not a fact, a point of view on what is a INT/LS (EX/LS) (hint: a core...)
steamroller has the same INT/LS (EX/LS) pair of core per module ... they just splitted the decode in 2 soooooo "2 INT/LS (EX/LS) 1 decode" is a single core and "2 INT/LS (EX/LS) 2 decode" is a dual core .... sooooo the core are defined by the decode unit? (hint they are not, that class action lawsuit was only a mean to cash on the fact that BD was slower than intel ... although on certain heavily threaded applications ... they weren't but those who use that wouldn't fill a class action lawsuit ... because it only really mattered in gaming performance ... thus: pissing in the wind)
soooo how about that non alcoholic beverage of your choice?
One question remains, how these court filling applied to, will it's applied to all Bulldozer uArch and derivatives?
If the article I linked to is accurate you can see which parts are included.