Wednesday, August 28th 2019
AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit
AMD reached a settlement in the Class Action Lawsuit filed against it, over alleged false-marketing of the core-counts of its eight-core FX-series processors based on the "Bulldozer" microarchitecture. Each member of the Class receives a one-time payout of USD $35 per chip, while the company takes a hit of $12.1 million. The lawsuit dates back to 2015, when Tony Dickey, representing himself in the U.S. District Court for the Northern District of California, accused AMD of false-marketing of its FX-series "Bulldozer" processor of having 8 CPU cores. Over the following four years, the case gained traction as a Class Action was built against AMD this January.
In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
Image Credit: Taylor Alger
Source:
The Register
In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
291 Comments on AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit
-> Processor models 00h–1Fh can perform an instruction block fetch every cycle, while model 30h–4Fh processors can perform a block fetch every 2 cycles.
-> In processor models 00h–1Fh, the decode unit scans two of these windows in a given cycle decoding a maximum of four instructions. In processor models 30–4Fh, the two decode units scan two of these windows every two cycles decoding a maximum of four instructions.
How is that a good change? It is two times slower than the previous generation.
Bulldozer fetches up to 32B every cycle.
Steamroller fetches up to 16B every cycle.
Bulldozer decodes up to 4 macro-instructions every cycle.
Steamroller decodes up to 2 macro-instructions every cycle.
Obviously, if AMD had decided to follow through with its original intention, it would have made Steamroller in no less than 8 core parts and wouldn't have cut away other things like cache. Steamroller was, obviously (as there was no 8-core part — not even a 6-core part), designed mainly to fit into the roles of reduced power consumption and reduced production cost. The minor IPC improvements from Steamroller and Excavator came at the cost of frequency and core count, both of which trumped the IPC gains in the high-performance realm — particularly when compared with mature-process Piledriver at performance-optimal clock, which is probably around 4.4 GHz. The designs were further hampered by an inferior socket/VRM spec and 28nm process.
www.anandtech.com/show/6201/amd-details-its-3rd-gen-steamroller-architectureIf they were really independent cores in the first place then this change wouldn't matter. Integer clusters aren't cores. They never were and they never will be.
one more timepoint... of... view...
nooowwww i think we all should stop ... because it's becoming ridiculous, i am right, seronx is right, you are right (ok in a 2:1 ratio about point of view but well can't have the same point of view ... right?)
oh man ... how much i would gladly pay to settle this (and keep my point of view on what define a core.)
• Neither were released in 6+ cores.
• Neither were released on a high-performance node.
• Neither were released on a high-performance VRM socket spec.
• Neither were released with high-performance amounts of cache.
Minor improvements to IPC pale in comparison to the lack of cores and frequency in Steamroller and Excavator, except in the niche they targeted where power consumption and cheap production cost were favored over performance.
An AMD Bulldozer/Piledriver/Steamroller/Excavator "module" is a "core" and AMD concurred by settling. 'nuff said.
as i said
A decode is not a feature of independent cores. The decode is independent of the cores. All of this is antagonistic to your reasoning. Which is more proof that the replicated parts in Bulldozer are in fact cores.
Minimal core is basically an ALU with a couple registers.
Realistically a core does need some control circuitry, this fits to things like Bulldozer parts or GPUs (CU, CUDA Core, EU).
In most literature this gets called execution core as its not all too useful by itself in a big complex processor and is part of execution stage or unit.
When talking about Bulldozer, the question boils down to expected functionality. What exactly should core be able to run?
- If it's what is generally referred to as micro-ops, then most pipes qualify as cores.
- In the way Bulldozer works, I think these were called macro-ops but if it needs some control, integer units qualify as cores. Technically, FP unit could qualify as well.
- If we want a core to run x86 instructions there really is no way around frontend.
None of these is wrong.
However every physical core has a control unit, an instruction bus, a data bus, and the datapath.
Buffer for inflight native bundles, scheduler to control all parts, a datapath to execute instructions, and a way to load and store data.
The global front-end also has the capability of Intel's "Anaphase". Which it can project a virtual core across all physical cores in the design as it contains a second-level control unit, instruction bus, data bus, but no physical datapaths.
Intel bought the company for cheap, from those that developed Pentium 3. So, the definition of a core is actually patented by Intel now.
Notice what is missing in this physical SMT4 quad-core with a single physical SMT4 core idled? That is right no decode!
I was looking through AMD Zen slides and came across this one:
Which reminded me of a diagram from the Hot Chips PDF:
Aren't they strikingly similar? Zen's picture is undeniably a "core" (see the last line on the right). It makes no sense to redefine what a "core" is for Bulldozer when it was well established before and after Bulldozer existed.
Even going all the way back to the original Pentium, instruction decoding was not decoupled from the core (because you'd have a calculator instead of a processor):
home.etf.rs/~vm/tutorial/micro/mps/mps.htm
FX-8350 is a quad-core, eight-thread processor. AMD simply choose to add a second integer cluster (and later a decoder) to accelerate the second thread. There's nothing wrong with that. What is wrong is that AMD misrepresented their product to the public.
I just leave this here....
www.extremetech.com/extreme/217672-analysis-amd-lawsuit-over-false-bulldozer-chip-marketing-is-without-merit
All of you naysayers keep repeating this over and over and yet all material out there disagrees with you. It's accepted that a core doesn't need to fetch, decode and execute instructions in it's own and can be something as simple as a SIMD unit. The only level at which fetching and decoding must happen (as in a requirement) is at the "processor" level which may or may not contain multiple cores.
I posed this question many times but I never got a definitive answer, are you telling me that the authors of the conjoined cores paper mislabeled the subject of their research ?
Were cores such as AMD's the norm ? No, but that doesn't they weren't part of this generic classification of "cores". Pointing fingers and saying this block does not look identical to this other block is a really, really primitive way of arguing about this. You are essentially throwing any information that goes more than skin deep out the window.
www.microarch.org/micro37/papers/18_Kumar-Conjoined-Core.pdf
Look at the title: "Conjoined-core Chip Multiprocessing"
If AMD put that on their box this suit wouldn't have happened.Hell no, paper was published in 2004. There's no record of the idea before that.
AMD's first dual-core debuted in 2005 and so did Intel's. Bulldozer is the only commercial conjoined-core chip to be sold and it didn't debut until 2011.