Wednesday, August 28th 2019
AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit
AMD reached a settlement in the Class Action Lawsuit filed against it, over alleged false-marketing of the core-counts of its eight-core FX-series processors based on the "Bulldozer" microarchitecture. Each member of the Class receives a one-time payout of USD $35 per chip, while the company takes a hit of $12.1 million. The lawsuit dates back to 2015, when Tony Dickey, representing himself in the U.S. District Court for the Northern District of California, accused AMD of false-marketing of its FX-series "Bulldozer" processor of having 8 CPU cores. Over the following four years, the case gained traction as a Class Action was built against AMD this January.
In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
Image Credit: Taylor Alger
Source:
The Register
In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
291 Comments on AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit
i5 6500 runs at 3200MHz all core and 3600MHz single core (12.5% faster). Take that into account and it scales perfectly - 3.99x - effectively 100%.
SMT and similar do increase performance over 100% per core.
Intel HT gives a 25-30% extra, Zen/Zen2 SMT gives 30-35%.
Bulldozer's CMT tends to give 60-65% ;)I don't know. Hoping some meaningful discussion comes out of this somehow? :)
Or at least we can learn something.
Really i dont understand the fuss from people. Yes it's a 4 core 8 thread CPU or a different approach to having SMT or some shit. It might not perform as it did but it did it's task. It was sufficient for the most tasks and esp hardcore rendering. Looking at the price point you coud'nt complain either. It was one of the CPU's that allowed them to OC all the way up to 5Ghz ~ 5.2Ghz. They where alot of fun to play with.
These days Intel locks their CPU's and AMD already pushes for max clocks using XFR. There is'nt that much fun in CPU world these days.
The front-end doesn't decide that thread A can run on core B, vice versa. The cores decide which thread runs on them and its hardlocked.
The scheduler unit, the 40-entry unified scheduler decodes macro-ops from the retire queue which can only be for one thread. Into, micro-ops to be executed within the superscalar datapath, which results can be stored into memory via the data bus.
None of this is controlled by the supposed shared front-end, all of this is handled purely by the core. Of which there are two cores in Bulldozer.
Edit: At the time I had a Phenom II x4 960T that unlocked to five cores. I was looking to replace the Phenom II but reviews for the new FX 8150 showed my slight overclock of 3.7 GHz Phenom II x5 was faster.
Later confirmed in some benchmarks I tested. I ended up moving to a Intel Xeon 1240 V2.
Fetch, decode and dispatch are frontend.
Did you look at the linked diagram?
Branches don't execute in the front-end, they execute in the cores.
Instructions are fetched and retired by the cores, not the front-end.
etc.
Whether the front-end was VMT2 with absolute competitive sharing or if it was Cluster-based multithreading with no sharing. Would not determine the amount of cores in the module.
Front end is part of core.
Fetch is at the very top of the diagram.
Retire... is not quite what you seem to think it is.
FE, L2, FPU => optional units.
Tell me, how many cores are there in a Zen CCX?
Also, is FPU a core or not?
A single Zen processor has a single core, there eight Zen processors which are eight cores. In a CCX there is four cores, thus four single-core monolithic processors.
However, a single Bulldozer processor has two cores, thus four Bulldozer processors are also eight cores.
Stoney, single dual-core monolithic processors => two cores
Carrizo, two dual-core monolithic processors => four cores
Kaveri, two dual-core monolithic processors => four cores
Trinty, two dual-core monolithic processors => four cores
Orochi, four dual-core monolithic processors => eight cores
Is there an OS (or software) that can run on RISC AMD64? Can such software be written?
Doesn't monolithic normally refer to a die?
Instruction bus => Retire queue
Control unit => Scheduler
Data bus => Load/store unit
Datapath => EX0/EX1/AGLU0/AGLU1
^-- easily defined a core.
When it comes to buses, it needs access to these and not much more, right?
When people don't understand, they are going are to see what they want to see regardless if the proof is right there in front of them. Also if you slice the second image horizontally across and swap the bottom and top then rotate the image 90 degrees it looks an awfully a lot like the first.
The secret sauce is that these are grouped in SMs which subsequently execute instructions , more specifically just one instruction, in groups of 32 because that's the only thing the control unit can do. It can't issue instructions to these cores independently because they can't do the fetch and decode or anything that has to do with control signals on their own. AMD does the same with their GPUs but at the very least they call them by the more generic label of "processors".
If anyone should be crucified for ambiguous and misleading labels, it should be Nvidia.
Big square blocks that are arranged symmetrically, preferably with a bright red border, that's the only definition that they'll accept for a core because that's the extent to which their understanding goes.
The problem with applying this to Bulldozer is that the resulting core is not exactly useful to us. AMD64 RISC is not exposed in any way. X86 goes out the window the moment you remove frontend.