Intel has today released the 43rd edition of its x86/x64 ISA developer manual designed to help developers see what's new in x86 world and make software optimizations for Intel's platform. In the latest edition of the manual, Intel has revealed the details of its low-power x86 "Tremont" architecture designed for 10 nm efficient, low-power computing. Announced last year in October, Intel promised to deliver a big IPC increase compared to the previous generation low-power CPU microarchitecture like the Goldmont Plus family. To achieve extra performance, Intel has implemented a lot of new solutions.

For starters, Tremont boasts better branch prediction unit, with increased capacity for instruction queue and better path-based conditional and indirect prediction. The front-end fetch and decode pipeline have been updated as well. Now the design is a 6-wide Out of Order Execution (OoOE) pipeline which can process 6 instructions per cycle. The Data cache is now upgraded to 32 KB. The load and store execution pipelines are now doubled and they are capable of two loads and two stores, or one load and one store, depending on the application. Tremont also updates on one important point and that is a dedicated store data port for integer and vector integer/floating-point data. Another big improvement is happening in the cryptography department. Tremont now features Galois-field instructions labeled as the GFNI family of instructions. There are two AES units for faster AES encryption and decryption. The already implemented SHA-NI cryptography standard was enhanced and it now is much faster as well. For mode in-depth report please check out Intel's x86/x64 manual.