ARFGood news:

wccftech.com/nvidia-geforce-rtx-3060-rtx-3050-ga106-ga107-ampere-gaming-gpu-specs-rumor/


This means these chips will be seen at least 6 months from now, most likely Q2 2021.

EarthDogWhy is that good news... if this is true...

I want these in 4Q...

The gamers hoping, wishing, and praying for a new generation of GeForce cards to arrive this week got some bad news from the company’s CEO during a Computex press briefing: The hardware won’t show up for a “long time.”

medi01Say, if stuff is to be released for CP2077, shouldn't RDNA2 cards be in full swing AIB production already? Yet, there have been no leaks so far.

Is it me or the gap between 3070Ti and 3080 is rather large?


This makes no sense. You get faster cycles (higher clocks) you don't miraculously get circuits that are capable of doing something in 1 cycle if it took 2.

ARFWell, Nvidia's CEO was right :)



Nvidia CEO: No next-gen GeForce GPUs for a 'long time,' but G-Sync BFGDs are coming soon
www.pcworld.com/article/3278095/no-geforce-gpus-g-sync-bfgds-nvidia.html


At that time I said don't expect RTX 3000 before H2 2020, most likely H1 2021.

EarthDogWhat does a long time mean?

RandallFlaggFaster transistor switching is not the same as higher clocks. And faster transistor switching does translate into potentially faster completion of instructions.

I'm not going to get into this with you people, just use google, there are dozens if not hundreds of references to this.

You might start here :

www.eeeguide.com/transistor-switching-times/

ARFYears. The quote is from Summer 2018.

EarthDoglol, I didn't catch that was from 2018, lol. What did you intend to convey with that? Nothing that matters for today?

ValantarI believe they are trying to say that the cards will launch at some point far from sumer 2018. I.e. a statement that without specific context and explanation could mean tomorrow or in ten years. Call me an optimist, but ersonally, I'm leaning towards it being a lot closer to tomorrow than ten years from now. More than two years is definitely a long time in the GPU world.

ValantarBut it can still only switch once per clock cycle, no? So faster switching speeds would help drive up clock speeds (as the time needed for a transistor to complete a cycle is shortened), but otherwise not change anything as a shorter time won't help do anything without a signal to make it do something. No?

RandallFlaggI don't think you're understanding what is happening. There are some entire microcode instructions that complete in one clock. In some cases, more than 1 instruction completes in a single clock *on average* because multiple instructions are being decoded at once (multiple pipelines). I

The speed that happens all comes down to transistor switching.

Look at this picture of a NAND gate. The 2nd transistor needs a result from the first to get an output. Now consider, a single micrcode instruction can have thousands of these gates (and other items like registers - storage locations - etc). If you make those gates switch faster for a given power input, you get a result faster. OR you can get the same performance at lower power because the instructions are completing faster.

Now you can make a transistor switch faster by giving it more power to overcome the impedance. This is why, when overclocking, it's common to hit a point where you have to increase voltage. The transistors need the extra power to keep up with the higher clocks.

This type of improvement is why you'll see TSMC stating things like getting a 20% improvement in performance from one node to another. That's an ideal situation for marketing purposes but the performance improvements are there.

ValantarBut again, all of that comes down to increased clock speeds, both your description of speeding up instruction decoding and the performance increases cited by foundries. When TSMC is talking about a 20% performance increase for a new node, they are talking about a 20% clock speed increase at the same power draw, as that is the only (somewhat) architecture-independent metric possible.

EarthDogAims at another goal post........

Ok....... that tells us nothing. What does a long time mean? Stop guessing ARFy...lol

mtcn77But, Nvidia doesn't ever tell you anything. That is what is missing.
Nvidia launches products.
They don't make industry progress. For instance, the same monitor interface data compression method would improve frame doubling pipelines had it been implemented in displays, however they don't develop for outside markets.

mtcn77But, Nvidia doesn't ever tell you anything. That is what is missing.
Nvidia launches products.
They don't make industry progress. For instance, the same monitor interface data compression method would improve frame doubling pipelines had it been implemented in displays, however they don't develop for outside markets.

EarthDog... I think I missed your point? We all know it's more of a closed ecosystem... but that has nothing to do with this discussion (at least what I'm talking about).

I'm simply wondering why the hell a 2 y.o article was used to..... I dont even know why tf it posted........and now here we are discussion whatever point has nothing to do with what i said... man I love TPU......... :ohwell:

ARFlol You said you want something in Q4, I told you to wait a bit longer. :D

EarthDogI think I missed your point?

mtcn77You missed the point on how industry's inflection point is Nvidia. Nvidia competes with monitor scaler manufacturers. There is no cooperation between them.
Think of it this way: LCD beats OLED in every manner apart from pixel transitions. That is what is important about the convention. At the advent of the VVC codec, this could tap into vrr methods. Lcds overdrive better if they get multiple frame signals. It is due to liquid crystal alignment, they get jumbled up if voltage applied is direct current.

RandallFlaggNo that is incorrect. You seem to think all instructions complete in one clock so everything is based on clock. They don't. Most instructions take multiple clocks and pass through tens if not hundreds of thousands of gates during that clock cycle, and typically *are not* complete in that clock cycle. If you make your gates switch quicker, you get the result faster, it is simple as that. You can do your own research, not going to waste more time here.

ValantarI didn't say instructions complete in a single cycle, just that I would assume that any increase in transistor switching speed is typically absorbed into the margins needed for increased clocks, meaning there is little room left for further utilizing this to lower the amount of cycles needed to finish an instruction. Some, sure, but a few percent isn't enough to allow you to finish in one cycle rather than two unless you were already very, very close to that target or you redesign the hardware to reach this goal, in which case one could argue that the increase in switching speed is less important than the redesign (though it obviously lowers the bar).

ValantarBut again, all of that comes down to increased clock speeds, both your description of speeding up instruction decoding and the performance increases cited by foundries. When TSMC is talking about a 20% performance increase for a new node, they are talking about a 20% clock speed increase at the same power draw, as that is the only (somewhat) architecture-independent metric possible.

AssimilatorThe cath?

EarthDog... then some shiza about NV monitor scaling and other things......?????????!!!!!!!!!??????????