AMD later this month is preparing to address investors as part of a yet-unknown event. The company typically hosts Financial Analyst Day events around Q1-Q2, and goes to the investors with substantial material on the current state of the organization, the products on offer, what's on the horizon, and how it could impact the company's financials. An alleged presentation related to the November 2021 event was leaked to the web. The presentation provides a guided tour of the entire product portfolio of the company, spanning server processors, compute accelerators, consumer graphics, some client processors, and the semi-custom business.

The presentation outlines that the company has so far successfully executed its roadmaps for the client-CPU, server-CPU, graphics, and compute-accelerator segments. In the client CPU segment, it shows a successful execution up to 2021 with the "Zen 3" microarchitecture. In the server space, it mentions successful execution for its EPYC processors up to "Zen 3" with its "Milan" processors, and confirms that its next-generation "Zen 4" microarchitecture, and its sister-architecture, the "Zen 4c," will be built on the 5 nm silicon fabrication node (likely TSMC N5). The presentation also details the recently announced "Milan-X" processor for existing SP3 platforms, which debuts the 3D Vertical Cache technology, bringing up to 96 MB of L3 cache per CCD, and up to 768 MB of L3 cache (804 MB L1+L2+L3 cache) per socket.Update 10:54 UTC: The presentation can now be found on the AMD Investor Relations website.

There were no disclosures made about next-generation client processors, neither in the desktop nor mobile markets. In the server space, however, AMD references "Genoa," its next-generation EPYC processor, which features up to 96 CPU cores, with DDR5 memory and PCIe Gen 5; as well as the "Bergamo" EPYC processors for the cloud-computing market, which dials up CPU core counts all the way up to 128. Both chips are based on "Zen 4." AMD also references its recently announced MI250 compute accelerators based on the CDNA2 architecture, which use compute dies built on the 6 nm node, an enhancement of TSMC N7.

The company also elaborate on how the Xilinx acquisition would go down, the key people involved in the transaction from both organizations, and how the resulting AMD-Xilinx combine would look. The transaction would end before December 31, with current Xilinx CEO Victor Peng taking over as the head of the Xilinx division under CEO Lisa Su. Devinder Kumar will continue as CFO. At least two directors of Xilinx would join the AMD Board.

The complete presentation follows.