Monday, February 28th 2022
Intel Unintentionally Shares 700-Series Chipset Spec
In an updated datasheet, which is currently still available online, Intel seemingly forgot to remove the specs of its upcoming Z790, H770 and B760 chipsets. The changes are fairly minor, although we obviously don't know if Intel are planning any changes on the CPU side in terms of connectivity. However, this is a surprising slipup from Intel's side and we've confirmed that the specs listed are indeed correct for the upcoming 700-series chipsets. The H610 chipset won't be getting an updated replacement though, but this seems to be par for course when it comes to Intel and its chipset updates.
Starting from the top, the Z790 chipset will see a move from 12 to 20 PCIe 4.0 lanes, while at the same time seeing a reduction in PCIe 3.0 lanes by half, from 16 to eight. Intel will also add an additional USB 3.2 Gen 2x2 (20 Gbps) lane. The H770 gets a bump from 12 to 16 PCIe 4.0 and drops from 12 to eight PCIe 3.0 lanes. Finally the B760 chipset gets a bump from six to 10 PCIe 4.0 lanes, but also has its PCIe 3.0 lane count cut in half, from eight to four. No other changes seem to be planned, at least not based on the Intel spec sheet. It's worth pointing out that we're talking maximum lane count here, since the HSIO is flexible and it's up to the motherboard makers how to implement the various options. Out of the 38 HSIO lanes, the Z690 chipset has 10 dedicated lanes for USB 3.2, with the rest supporting PCIe in combination with either SATA and/or Gigabit Ethernet on a further 10 and this doesn't seem to change for the Z790 chipset.
Sources:
Intel, via @unikoshardware
Starting from the top, the Z790 chipset will see a move from 12 to 20 PCIe 4.0 lanes, while at the same time seeing a reduction in PCIe 3.0 lanes by half, from 16 to eight. Intel will also add an additional USB 3.2 Gen 2x2 (20 Gbps) lane. The H770 gets a bump from 12 to 16 PCIe 4.0 and drops from 12 to eight PCIe 3.0 lanes. Finally the B760 chipset gets a bump from six to 10 PCIe 4.0 lanes, but also has its PCIe 3.0 lane count cut in half, from eight to four. No other changes seem to be planned, at least not based on the Intel spec sheet. It's worth pointing out that we're talking maximum lane count here, since the HSIO is flexible and it's up to the motherboard makers how to implement the various options. Out of the 38 HSIO lanes, the Z690 chipset has 10 dedicated lanes for USB 3.2, with the rest supporting PCIe in combination with either SATA and/or Gigabit Ethernet on a further 10 and this doesn't seem to change for the Z790 chipset.
29 Comments on Intel Unintentionally Shares 700-Series Chipset Spec
I needed to learn more to avoid mistakes in future.
The bottom line for current Thunderbolt connections is that it is good for 10 GbE networking on 2 metre distance with copper cable and for external storage and hubs.
Thunderbolt is not good for monitors as it still does not support VRR/Gsync/FreeSync pass-through, and most adapter cables do not support it either. Intel's TB spec does not explicitly state that TB chip supports AdaptiveSync from DP spec. Finally, Gsync and FreeSync work over DP (including usb-c) and HDMI interfaces only.
Do not hold your breath for TB5 paired with monitors. To support variable refresh rate, gaming community needs to openly challenge Intel to implement it. Even Apple has problems with AdaptiveSync in their ecosystem over tunnelled DP inside TB. Apple will aim to enable full USB4 to get their head around it. "Fully-fat" USB4 implementation can work better than Thunderbolt.