Monday, February 28th 2022
Intel Unintentionally Shares 700-Series Chipset Spec
In an updated datasheet, which is currently still available online, Intel seemingly forgot to remove the specs of its upcoming Z790, H770 and B760 chipsets. The changes are fairly minor, although we obviously don't know if Intel are planning any changes on the CPU side in terms of connectivity. However, this is a surprising slipup from Intel's side and we've confirmed that the specs listed are indeed correct for the upcoming 700-series chipsets. The H610 chipset won't be getting an updated replacement though, but this seems to be par for course when it comes to Intel and its chipset updates.
Starting from the top, the Z790 chipset will see a move from 12 to 20 PCIe 4.0 lanes, while at the same time seeing a reduction in PCIe 3.0 lanes by half, from 16 to eight. Intel will also add an additional USB 3.2 Gen 2x2 (20 Gbps) lane. The H770 gets a bump from 12 to 16 PCIe 4.0 and drops from 12 to eight PCIe 3.0 lanes. Finally the B760 chipset gets a bump from six to 10 PCIe 4.0 lanes, but also has its PCIe 3.0 lane count cut in half, from eight to four. No other changes seem to be planned, at least not based on the Intel spec sheet. It's worth pointing out that we're talking maximum lane count here, since the HSIO is flexible and it's up to the motherboard makers how to implement the various options. Out of the 38 HSIO lanes, the Z690 chipset has 10 dedicated lanes for USB 3.2, with the rest supporting PCIe in combination with either SATA and/or Gigabit Ethernet on a further 10 and this doesn't seem to change for the Z790 chipset.
Sources:
Intel, via @unikoshardware
Starting from the top, the Z790 chipset will see a move from 12 to 20 PCIe 4.0 lanes, while at the same time seeing a reduction in PCIe 3.0 lanes by half, from 16 to eight. Intel will also add an additional USB 3.2 Gen 2x2 (20 Gbps) lane. The H770 gets a bump from 12 to 16 PCIe 4.0 and drops from 12 to eight PCIe 3.0 lanes. Finally the B760 chipset gets a bump from six to 10 PCIe 4.0 lanes, but also has its PCIe 3.0 lane count cut in half, from eight to four. No other changes seem to be planned, at least not based on the Intel spec sheet. It's worth pointing out that we're talking maximum lane count here, since the HSIO is flexible and it's up to the motherboard makers how to implement the various options. Out of the 38 HSIO lanes, the Z690 chipset has 10 dedicated lanes for USB 3.2, with the rest supporting PCIe in combination with either SATA and/or Gigabit Ethernet on a further 10 and this doesn't seem to change for the Z790 chipset.
29 Comments on Intel Unintentionally Shares 700-Series Chipset Spec
I wonder if AMD X670 will have native USB4 as standard, or if manufacturers will have the choice not to include a USB4 port, similar to the Intel side where manufacturers offer TB4 on some of their SKUs but not all...
Considering their Zen3+ notebook chips already has support for it, I would expect AM4 CPUs to support it, but maybe not the chipset. Currently shipping laptops are said to be missing firmware and UEFI/AGESA support, but it should be enabled at some point in the future.
without the ic got upgraded to gen4 edition, the same amount of lanes are needed no matter gen3 or gen4 lanes are used to feed that ic.
the only gen4 ic i can recall now, is the 10g lan chip(4.0x1) , but current z690s with 10g lan chip used are mostly gen3 edition, namely x2 is needed.
PCIe 4.0 goes from 6 to 10, so plus 4.
And it was of course supposed to be B760, so fixed that typo.
That's the whole point of this new post.
Nothing to do with the CPUs.
600/700 chipset for laptops also does not need native USB4, as mobile CPU supports 4xTB4 ports on die. It's up to OEM to enable as many as they find suitable, usually two or three.
So, by having TB4 on a system, you already have USB4. TB4 is a better version of USB4 and USB4 is based on TB.
By analogy, both X570 and B550 can support USB4 if AMD partners bake Thunderbolt 4 chip, which a few OEMs have done, such as Asus ProArt Creator motherboards.
FP7 chipset on Rembrandt mobile CPUs support USB4 40 Gbps on die. X670 and B650 will support USB4 at 20 or 40 Gbps. Minimum PC speed is 20 Gbps and 10 Gbps for USB devices.
If however USB4 (or TB4) was embedded into the chipset or cpu then it would be a standard feature of z790. Instead, the standard usb-c solution of intel Z chipsets (Z590, Z690, and now Z790) is USB3.2x2 which is 20 Gbps but differs from USB4 in that it doesn’t support PCIe tunneling. So the native solution is kind of useless in my opinion. Because most storage devices top out at usb3 10 gbps… and if your usb-c device uses PCIE tunneling (nvme storage, 10gbps lan adapter, audio interface, egpu) then you still need TB. So from my point of view, 1 guaranteed USB4 port would be great… instead you have to shell more $$$ for a mobo with TB4 (maple ridge).
And the other issue is prior to Titan ridge, Intel TB solutions did not have a USB3.x fallback mode. Meaning that with an Alpine ridge controller for example (which is the controller of choice in many external nvme solutions) if you plug the device into a standard usb 3.x port, it doesn’t function. But it would function if plugged into a USB4 port (because of backwards compatibility with TB3). So even with the usb3.2x2 port on Z690 or z90, it is useless if you connect an Alpine Ridge device to it.
Given the optional nature of TB4 (and thus USB4) on Intel chipsets, I was simply wondering how AMD will implement USB4 on its upcoming chipset. Whether it will be standard unlike on Intel. Don’t know. Waiting to see.
They didnt call it a leak this time around! We're moving up in the gramur usage! :p
Intel reusing motherboard pin out "cutting corners".
*OEM CPU firmware lock something or other notwithstanding; but that's an edge case.
Source: www.tripplite.com/products/thunderbolt-4
Also, TB4 has 100W power delivery, USB4 with Extended power range is capable to deliver up to 240W.
Source: en.wikipedia.org/wiki/USB4#Data_transfer_modes
That out of the way looks like x4 lanes coming off the CPU and x4 being Frankensteined from PCIE 3.0 lanes into PCIE 4.0 lanes with x4 out of the x8 additonal PCIE 4.0 lanes going to USB 3.2 Gen 2x2 (20Gbps) ports. Which seems good more flexibility for the PCIE 4.0 lanes towards multi-gpu configurations or additional PCIE 4.0 NVME devices among other possibilities.
On TB4, PCIe 3.0 transfer speed is just shy of ~3 GB/s, which is similar to good NVMe drives running at 3.0 speed x4 in external enclosure with TB4 chip and interface. The main difference is that PCIe 3.0 x4 is obligatory on TB4, whereas on USB4 host device 40 Gbps link, PCIe and TB Alt tunneling are only optional, so OEMs have three choices:
1. install Maple Ridge TB4 chip on either Intel or AMD motherboards to get all features above - cost up
2. install minimal USB4 chip for Rembrandt APUs with 20 Gbps link - PD 3.0/3.1, USB data 10 Gbps, DP 1.4 tunneling and DP Alt minimum 1.4
3. install full fat USB4 chip for Rembrandt APUs with 40 Gbps link - PD 3.0/3.1, USB data 20 Gbps, PCIe data, DP 1.4 tunneling and DP 2.0 Alt at 40 Gbps
* it should be checked whether both USB4 controllers are available. I have only seen VL830 for hubs, which does not support PCIe.
Also, if OEMs decide to tunnel PCIe data over USB4, they need to wire it, which is usually 3.0 x4 or 4.0 x4. So, PCIe over one USB4 port will effectively be at 32 Gbps with overhead and not 40 Gbps, or 64 Gbps split between two ports (some laptops with Rembrandt APUs).
*For Rembrandt APU, PCIe 4.0 wiring for USB4 is x4. APUs have x4 general purpose 4.0 lanes, so x2 for one USB4 port or x4 for two USB4 ports, if OEMs certify one or two ports and add PCIe tunneling. Those APUs also support DP 2.0 at 40 Gbps on die. If all features are implemented, this would be "TB4 plus", due to DP 2.0 and PCIe 4.0. Intel is aiming to match and surpasss this with TB5, where DP 2.0 will have 80 Gbps.
Current evolution of high-speed, multi interface looks like this:
1. TB4 chip - PCIe 3.0 at 32 Gbps, USB 10 Gbps, DP 1.4 at 32 Gbps and PD 3.0 100W+15W, can tunnel two displays
2. USB4 chip-PCIe 4.0 at 64 Gbps (two ports, each 32), USB 20 Gbps, DP 1.4 tunnel at 32 Gbps, DP 2.0 Alt at 40 Gbps and PD 3.1 up to 240W, can tunnel one display
3. TB5 chip - PCIe 5.0 at 128 Gbps (two ports, each 64), USB 20 Gbps, DP 2.0 host at 80 Gbps and PD 3.1 240W, can tunnel two or more displays
* For TB5 chips on desktop PC, Intel would first need to enable PCIe 5.0 lanes on DMI link and in the chipset, so that TB5 chips can take advantage. Not on Z790 platform. They will first enable TB5 on die for laptop CPUs starting with Meteor Lake or later, as their CPUs support PCIe 5.0. Step by step.
Recent power delivery PD 3.1 revision indeed introduced up to 240W, but this is highly unlikely to be found in any PC desktop host. This solution is for laptops and docking stations/hubs, whereas charging from USB4 port on desktop host will mostly be limited to PD 3.0 chips, up to 100W. It seems that 240W of charging power on desktop motherboard could only be on rare halo models, as it will drive costs to isolate heat.True. On desktop, not all motherboards need TB4 chips and it is right to leave it to OEMs to decide, depending on market they target with specific motherboards.True. USB Implementers Forum came to compromize with OEMs and did not mandate PCIe tunneling. They also wanted USB4 to be a bit different from TB. Intel mainstream desktop CPUs do not support USB from processors, only from chipset. AMD CPUs do and it is easier for Ryzen to support USB4 from CPU.
Z790 chipset could add USB4 natively, but this remains to be seen, as they already have TB4 chips and TB5 is in development.USB4 is already supported on Rembrandt platform, if OEMs decide to install a controller. So, up to 40 Gbps, could pair with PCIe 4.0 GPP and DP 2.0 Alt Mode and DP 1.4 tunneling form iGPU. This will also come to Zen 4 platform. It's a full scale USB4 enablement, but only on certified devices and if OEMs decide to utilize it. CPU is fully capable for USB4 and DP 2.0. It remains to be seen which OEMs decide to implement it, and how.That was unfortunate, but predicted by the spec.
JHL6240 chip provided USB downstream port, without compatibility for USB devices.
JHL6340 chip provided USB host port compatible for USB devices.
JHL6540 chip provided both host port and downstream port from peripherals that support USB devices, but are more expensive.
JHL6240 is the cheapest chip. I am not surprised that NVMe external storage vendors install this one. They should clearly say to buyers that connecting such device with USB port on the host system will not work if the host system does not have at least the same TB3 chip.