Friday, April 5th 2024
AMD Zen 5 Execution Engine Leaked, Features True 512-bit FPU
AMD "Zen 5" CPU microarchitecture will introduce a significant performance increase for AVX-512 workloads, with some sources reported as high as 40% performance increases over "Zen 4" in benchmarks that use AVX-512. A Moore's Law is Dead report detailing the execution engine of "Zen 5" holds the answer to how the company managed this—using a true 512-bit FPU. Currently, AMD uses a dual-pumped 256-bit FPU to execute AVX-512 workloads on "Zen 4." The updated FPU should significantly improve the core's performance in workloads that take advantage of 512-bit AVX or VNNI instructions, such as AI.
Giving "Zen 5" a 512-bit FPU meant that AMD also had to scale up the ancillaries—all the components that keep the FPU fed with data and instructions. The company therefore increased the capacity of the L1 DTLB. The load-store queues have been widened to meet the needs of the new FPU. The L1 Data cache has been doubled in bandwidth, and increased in size by 50%. The L1D is now 48 KB in size, up from 32 KB in "Zen 4." FPU MADD latency has been reduced by 1 cycle. Besides the FPU, AMD also increased the number of Integer execution pipes to 10, from 8 on "Zen 4." The exclusive L2 cache per core remains 1 MB in size.
Update 07:02 UTC: Moore's Law is Dead reached out to us and said that the slide previously posted by them, which we had used in an earlier version of this article, is fake, but said that the information contained in that slide is correct, and that they stand by the information.
Source:
Moore's Law is Dead (YouTube)
Giving "Zen 5" a 512-bit FPU meant that AMD also had to scale up the ancillaries—all the components that keep the FPU fed with data and instructions. The company therefore increased the capacity of the L1 DTLB. The load-store queues have been widened to meet the needs of the new FPU. The L1 Data cache has been doubled in bandwidth, and increased in size by 50%. The L1D is now 48 KB in size, up from 32 KB in "Zen 4." FPU MADD latency has been reduced by 1 cycle. Besides the FPU, AMD also increased the number of Integer execution pipes to 10, from 8 on "Zen 4." The exclusive L2 cache per core remains 1 MB in size.
63 Comments on AMD Zen 5 Execution Engine Leaked, Features True 512-bit FPU
It is pre-emptive to cry about wasted area.
Thanks to AMD, all that is thankfully over now, although it seems Intel has gone back to just bumping clocks and "gluing" on more cores on again.
One would think this would've been a career ending event to a leaker, but turns out his followers only grew in number since then. What the hell.
The main difference now is you have AI. A use and justification for special instruction sets.
Denser process with less leakage allow you to design much more complex execution units. Those can perform better that the same clock and clock higher. It's one of the reason why cache size have stayed in the same ballpark.
I mean clawhammer (Athlon 64) had 1 MB of L2 in 2003. Cache are a cycle and it's what they put when they can't just put a beefier execution unit or front end.
Ah, found it.