Qualitas Semiconductor Co., Ltd. has developed a new PCIe 6.0 PHY IP, marking a significant advance in computer interconnect technology. This new product, created using advanced 5 nm process technology is designed to meet the high-speed data transfer needs of the AI era. The Qualitas' PCIe PHY IP using 5 nm FinFet CMOS technology consists of hardmacro PMA and PCS compliant to PCIe Base 6.0 specification.

The PCIe 6.0 PHY IP can achieve transmission speeds up to 64GT/s per lane. When using all 16 lanes, it can transfer data at rates up to 256 GB/s. These speeds make it well-suited for data centers and self-driving car technologies, where rapid data processing is essential. Qualitas achieved this performance by implementing 100G PAM4 signaling technology. Highlighting the importance of the new IP, Qualitas CEO Dr. Duho Kim signaled the company's intent to continue pushing boundaries in semiconductor technology.Key Features

• 5 nm low power enhanced CMOS device technology
• 1.8 V ± 5%, 0.85 V ± 5% dual power supply
• Compliant to PCIe Base 6.0 and PIPE 6.1 specification
• Support Gen 1, Gen 2, Gen 3, Gen 4, Gen 5 and Gen 6
• Channel Configuration for Data Lanes
• Common (CMN) and 1, 2 or 4 Data Lanes
• Support the following transmitter pre-emphasis levels
• -3.5 / -6dB for Gen 1 and Gen 2
• Multi-tap FIR with resolution of 1/63 for Gen 3 to Gen 6
• Support CTLE, DSP-based multi-tap FFE and 1-tap DFE for channel equalization in receiver
• Support adaptive channel equalization
• 100 MHz reference clock is required (Support differential input buffer)
• Built-in self test feature capable of generating and checking PRBS patterns
• PCS included in PHY hardmacro