We are days away from the official November 7 launch of AMD's Ryzen 7 9800X3D CPU with 3D V-Cache, and we are already seeing some estimates of the speedup compared to the last-generation Ryzen 7 7800X3D CPU. According to a Geekbench submission discovered by Everest (Olrak29_) on X, the upcoming AMD Ryzen 7 9800X3D has been spotted running at a clock speed of 5.46 GHz. This is a 260 MHz increase from the official boost frequency of 5.2 GHz, which indicates overclocking has been applied. If readers recall, the last generations of X3D processors had overclocking disabled, and this time, things are looking different thanks to the compute die being placed on top of SRAM. AMD attributes this to CCD being closer to the heat spreader instead of memory and allowing it to spread heat more effectively, ensuring a stable overclock.

Regarding performance, the Ryzen 7 9800X3D outperforms its predecessor, the Ryzen 7 7800X3D, by an impressive 27.4% in the single-core Geekbench v6 test and 26.8% in the multicore test. The last generation CPU scored 2,726 points in single-core and 15,157 points in multicore tests, while the new Zen 5 design has managed to produce 3,473 points in single-core and 19,216 in multicore tests. These results are approximately 27% improvement over the Zen 4, suggesting that the Zen 5 architecture benefits greatly from better SRAM bandwidth and capacity. While these results only come from synthetic benchmarks, they give us a picture of what to expect from this CPU. We have to wait for more real-world test cases to fully conclude the improvement factor.

MSI is thrilled to introduce the upcoming AMD Ryzen 7 9800X3D, an innovation built on the Zen 5 architecture and featuring AMD's groundbreaking 3D V-Cache technology. The Ryzen 7 9800X3D is designed for peak performance with improved IPC and superior power efficiency compared to the previous generation, promising an exhilarating leap in computing power.

The Ryzen 7 9800X3D integrates seamlessly with the AM5 socket ecosystem, providing users access to PCIe Gen 5 bandwidth and high-speed DDR5 memory support. Built on a 4 nm process, this processor establishes a new performance, power efficiency, and responsiveness benchmark, ideal for intensive gaming and content creation. MSI's X870(E) motherboards are fully compatible with the Ryzen 7 9800X3D, featuring a robust lineup from MEG X870E GODLIKE to MAG X870 TOMAHAWK WIFI. MSI's X870(E) motherboards and AMD's latest processors unlock peak gaming performance for users.

Samsung is currently mass-producing its 9th generation V-NAND flash memory chips with 286 layers unveiled this April. According to the Korean Economic Daily, the company targets V-NAND memory chips with at least 400 stacked layers by 2026. In 2013, Samsung became the first company to introduce V-NAND chips with vertically stacked memory cells to maximize capacity. However, stacking beyond 300 levels proved to be a real challenge with the memory chips getting frequently damaged. To address this problem, Samsung is reportedly developing an improved 10th-generation V-NAND that is going to use the Bonding Vertical (BV) NAND technology. The idea is to manufacture the storage and peripheral circuits on separate layers before bonding them vertically. This is a major shift from the current Co-Packaged (CoP) technology. Samsung stated that the new method will increase the density of bits per unit area by 1.6 times (60%), thus leading to increased data speeds.

Samsung's roadmap is truly ambitious, with plans to launch the 11th generation of NAND in 2027 with an estimated 50% improvement in I/O rates, followed by 1,000-layer NAND chips by 2030. Its competitor, SK hynix, is also working on 400-layer NAND aiming to have the technology ready for mass production by the end of 2025, as we previously mentioned in August. Samsung, the current HBM market leader with a 36.9% market share have also plans for its DRAM sector intending to introduce the sixth-generation 10 nm DRAM, or 1c DRAM by the first half of 2025. Then we can expect to see Samsung's seventh-generation 1d nm (still on 10 nm) in 2026, and by 2027 the company hopes to release its first generation sub-10 nm DRAM, or 0a DRAM memory that will use a Vertical Channel Transistor (VCT) 3D structure similar to what NAND flash utilizes.

Motion Twin, of Dead Cells fame, has announced the early access release date for its next roguelite, Windblown, which looks to be a much more cheerful affair than the grim-dark Dead Cells, and it's designed for multiplayer, too. Windblown will feature many of the same gameplay elements as Dead Cells, though, including fast-paced hack-and-slash combat, platforming, and permanent death. This time, though, Motion Twin has gone for an isometric perspective, instead of the side-scroller style, and the pixel graphics are swapped out for a cutesy cartoon style and color palette somewhat reminiscent of the likes of Paladins. There also appear to be some nifty bullet-hell-style battles thrown into the mix.

As for the release date and playable demo, Motion Twin has not yet announced when the game will fully release, but a Windblown demo will launch on October 14 during the upcoming Steam Next Fest, and Steam Early Access for the full game arrives on October 24. Motion Twin also says that any progress and unlocks achieved during the playable demo will carry over once the full game launches, which is a nice touch.

AVer Information Europe B.V. is proud to introduce the FONE700, a cutting-edge ceiling-mounted speakerphone designed to transform hybrid meetings by delivering superior audio quality and seamless video integration. Poor audio often hampers virtual communication, but the FONE700 solves this issue with 360-degree audio coverage, ensuring participants can be heard clearly, no matter where they are in the room.

Clear Audio, Clutter-Free Design
The FONE700's ceiling-mounted design provides a clean, professional look while offering better sound quality than traditional table-top speakerphones. By elevating the microphone and speaker, it removes the need for participants to cluster around a central device, delivering consistent, crisp audio throughout the room.

Microsoft's Direct3D and HLSL teams have unveiled plans to integrate SPIR-V support into DirectX 12 with the upcoming release of Shader Model 7. This significant transition marks a new era in GPU programmability, as it aims to unify the intermediate representation for graphical-shader stages and compute kernels. SPIR-V, an open standard intermediate representation for graphics and compute shaders, will replace the proprietary DirectX Intermediate Language (DXIL) as the shader interchange format for DirectX 12. The adoption of SPIR-V is expected to ease development processes across multiple GPU runtime environments. By embracing this open standard, Microsoft aims to enhance HLSL's position as the premier language for compiling graphics and compute shaders across various devices and APIs. This transition is part of a multi-year development process, during which Microsoft will work closely with The Khronos Group and the LLVM Project. The company has joined Khronos' SPIR and Vulkan working groups to ensure smooth collaboration and rapid feature adoption.

While the transition will take several years, Microsoft is providing early notice to allow developers and partners to plan accordingly. The company will offer translation tools between SPIR-V and DXIL to facilitate a gradual transition for both application and driver developers. For those not familiar with graphics development, graphics APIs ship with virtual instruction set architectures (ISA) that abstracts standard hardware features at a higher level. As GPUs don't follow the same ISA as CPUs (x86, Arm, RISC-V), this virtual ISA is needed to define some generics in the GPU architecture and allow various APIs like DirectX and Vulkan to run. Instead of focusing support on several formats like DXIL, Microsoft is embracing the open SPIR-V standard, which will become de facto for API developers in the future, allowing focus on more features instead of constantly replicating each other's functions. While DXIL is used mainly for gaming environments, SPIR-V has adoption in high-performance computing as well, with OpenCL and SYCL. Gaming presence is also there with Vulkan API, and we expect to see SPIR-V join DirectX 12 games.

Japanese professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has unveiled a revolutionary extreme ultraviolet (EUV) lithography technology that promises to significantly push down semiconductor manufacturing costs. The new technology tackles two previously insurmountable issues in EUV lithography. First, it introduces a streamlined optical projection system using only two mirrors, a dramatic simplification from the conventional six or more. Second, it employs a novel "dual line field" method to efficiently direct EUV light onto the photomask without obstructing the optical path. Prof. Shintake's design offers substantial advantages over current EUV lithography machines. It can operate with smaller EUV light sources, consuming less than one-tenth of the power required by conventional systems. This reduction in energy consumption also reduces operating expenses (OpEx), which are usually high in semiconductor manufacturing facilities.

The simplified two-mirror design also promises improved stability and maintainability. While traditional EUV systems often require over 1 megawatt of power, the OIST model can achieve comparable results with just 100 kilowatts. Despite its simplicity, the system maintains high contrast and reduces mask 3D effects, which is crucial for attaining nanometer-scale precision in semiconductor production. OIST has filed a patent application for this technology, with plans for practical implementation through demonstration experiments. The global EUV lithography market is projected to grow from $8.9 billion in 2024 to $17.4 billion by 2030, when most nodes are expected to use EUV scanners. In contrast, ASML's single EUV scanner can cost up to $380 million without OpEx, which is very high thanks to the power consumption of high-energy light UV light emitters. Regular EUV scanners also lose 40% of the UV light going to the next mirror, with only 1% of the starting light source reaching the silicon wafer. And that is while consuming over one megawatt of power. However, with the proposed low-cost EUV system, more than 10% of the energy makes it to the wafer, and the new system is expected to use less than 100 kilowatts of power while carrying a cost of less than 100 million, a third from ASML's flagship.

Fractal Design has released the 3D printing files for their highly sought-after Raspberry Pi case, dubbed Project: North Pi. The tiny case, which caused a sensation at this year's Computex trade show, can now be produced by anyone with access to a 3D printer. The Project: North Pi case first caught the public's eye during Fractal Design's product launch at Computex, where it was used as a playback device alongside a mini computer. Its diminutive size and sleek design, reminiscent of the company's North series, quickly captured the imagination of attendees and media alike. The case's popularity even threatened to overshadow Fractal Design's other new products, including the Mood ITX case, Refine office chair, and Scape headset. Following the overwhelmingly positive response, Fractal Design has decided to share the case's design with the public.

The company has published a dedicated product page containing free downloadable files and comprehensive instructions for 3D printing the case at home. The Project: North Pi case consists of 17 components (11 unique parts) and measures a compact 105 × 50 × 96 mm size. Despite its tiny nature, the case includes space for up to two 40 mm fans behind its front panels, ensuring adequate cooling for the Raspberry Pi. This move by Fractal Design caters to the DIY community and represents a shift in how companies might approach product distribution in the future. By embracing 3D printing technology, Fractal Design has effectively turned its customers into manufacturers, potentially changing the way enthusiasts interact with and customize their tech accessories. As the 3D printing community eagerly begins to produce their own Project: North Pi cases, we wait to see different color combinations and use cases from enthusiasts.

Gigabyte has quietly added a new SSD to its growing lineup and this time around it's something quite different. The drive is part of Gigabyte's new AI TOP (Trillions of Operations per Second) and was announced at Computex with little fanfare. At the show, the company only announced that it would have 150x the TBW compared to regular SSDs and that it was built specifically for AI model training. What that 150x means in reality is that the 2 TB version of the AI TOP 100E SSD will deliver no less than 219,000 TBW (TeraBytes Written), whereas most high-end 2 TB consumer NVMe SSDs end up somewhere around 1,200 TBW. The 1 TB version promises 109,500 TBW and both drives have an MTBF time of 1.6 million hours and a five-year warranty.

Gigabyte didn't reveal the host controller or the exact NAND used, but the drives are said to use 3D NAND flash and both drives have a LPDDR4 DRAM cache of 1 or 2 GB depending on the drive size. However, the pictures of the drive suggest it might be a Phison based reference design. The AI TOP 100E SSDs are standard PCIe 4.0 drives, so the sequential read speed tops out at 7,200 MB/s with the write speed for the 1 TB SKU being up to 6,500 MB/s, with the 2 TB SKU slightly behind at 5,900 MB/s. No other performance figures were provided. The drives are said to draw up to 11 Watts in use, which seems very high for PCIe 4.0 drives. No word on pricing or availability as yet.

At Computex 2024, Colorful has launched an ultra-exclusive new graphics card - the iGame Lab 4090. This limited edition GPU is squarely targeted at hardcore overclockers and performance enthusiasts willing to pay top dollar for the absolute best. With only 300 units produced globally, the iGame Lab 4090 represents the pinnacle of Colorful's engineering efforts. Each chip was hand-selected from thousands after rigorous binning to ensure premium silicon capable of extreme overclocks. The card's striking aesthetics feature a clean white shroud with silver accent armor. Beyond the intricate design, the real draw is performance. The iGame Lab 4090 has already shattered records, with professional overclocker CENs pushing it past 3.8 GHz under 3D load. It set a new world record 3DMark Time Spy Extreme score of 24,103 points. Out of the box, the card features a base clock of 2235 MHz, a boost clock of 2520 MHz, and a turbo mode of 2625 MHz, all while being a 3-slot design.

Asetek, innovator of gaming hardware for next-level immersive gaming experiences and the creator of the all-in-one (AIO) liquid cooler, today announced a strategic partnership with Fabric8labs, a leading innovator in metal 3D printing. This exclusive partnership with Fabric8Labs covers the commercial and consumer desktop markets and introduces a revolutionary advancement in liquid cooling technology, showcased in the AI Optimized Cold Plate. Leveraging Fabric8Labs' cutting-edge Electrochemical Additive Manufacturing (ECAM) technology, Asetek has developed a cold plate design that will redefine industry leading performance.

The partnership embodies a shared commitment to innovation that drives superior performance, high quality, and lasting reliability. The AI Optimized Cold Plate demonstrates a significant improvement over previous generations, highlighting the effectiveness of this collaboration. Fabric8Labs' unique 3D printing technology plays a pivotal role in this innovation. Their ECAM method allows for the creation of complex, high-resolution structures that significantly improve thermal capabilities through enhanced fluid dynamics. Also, by eliminating the need for post-processing, ECAM ensures the highest quality and integrity of each cold plate and is massively scalable to support high-volume production demands.

It'd be fair to say Final Fantasy VII Rebirth's next-gen makeover of characters, monsters, and more from the 1997 original has been a spectacular glow-up. The modern console era has returned an iconic cast and world to us with a level of realism in gameplay that even pre-rendered cutscenes over 25 years ago couldn't match. We asked Square Enix if they could crunch some numbers and share some insight into the changes nearly three decades of technological advancement have wrought. Here, main character modeler and lead character artist Dai Suzuki walks us through a selection of characters, creatures, weapons, and more.

Dai Suzuki: When people think of Cloud, most think of his gigantic sword and his unique hairstyle. Because it is so iconic, we needed to put special effort into creating Cloud's hair for Final Fantasy VII Remake, to properly express his personality. The hair was an extremely high-priority element and in fact accounted for half of the total polygon count for the whole model. In Final Fantasy VII Rebirth, the hardware has been changed to PS5, allowing for a higher polygon count to be used than in Final Fantasy VII Remake.

3DMakerpro, a pioneer in consumer-friendly 3D scanning technology, announces the launch of the Moose Series, beginner-friendly 3D scanners with AI visual tracking technology. The Moose series is 3DMakerpro's latest consumer-grade 3D scanner line-up offering, designed to handle real-world medium-sized objects into 3D models with remarkable efficiency and precision. Powered by a set of AI features and in collaboration with Oqton, developers of Geomagic Wrap, 3DMakerpro aspires to make 3D scanning easier and more accessible to beginners and advanced users in the creative field.

"The Moose series brings consumer 3D scanning to new heights of accuracy and allows more users to benefit from the convenience of 3D scanning," said Tianshi Yuwen, Global Marketing Director of 3DMakerpro. "Our dedication to innovation empowers us to democratize high-precision 3D scanning and push beyond the boundaries of making all creative visions a reality."

NVIDIA has been offering its GPU IP for more than a decade now ever since the introduction of Kepler uArch, and its IP has had relatively low traction in other SoCs. However, that trend seems to be reaching an inflection point as NVIDIA has given MediaTek a license to use its GPU IP to produce the next generation of processors for the auto industry. The newest MediaTek Dimensity Auto Cockpit family consists of CX-1, CY-1, CM-1, and CV-1, where the CX-1 targets premium vehicles, CM targets medium range, and CV targets lower-end vehicles, probably divided by their compute capabilities. The Dimensity Auto Cockpit family is brimming with the latest technology, as the processor core of choice is an Armv9-based design paired with "next-generation" NVIDIA GPU IP, possibly referring to Blackwell, capable of doing ray tracing and DLSS 3, powered by RTX and DLA.

The SoC is supposed to integrate a lot of technology to lower BOM costs of auto manufacturing, and it includes silicon for controlling displays, cameras (advanced HDR ISP), audio streams (multiple audio DSPs), and connectivity (WiFi networking). Interestingly, the SKUs can play movies with AI-enhanced video and support AAA gaming. MediaTek touts the Dimensity Auto Cockpit family with fully local AI processing capabilities, without requiring assistance from outside servers via WiFi, and 3D spatial sensing with driver and occupant monitoring, gaze-aware UI, and natural controls. All of that fits into an SoC fabricated at TSMC's fab on a 3 nm process and runs on the industry-established NVIDIA DRIVE OS.

Japanese tech giant Canon hopes to shake up the semiconductor manufacturing industry by shipping new low-cost nanoimprint lithography (NIL) machines as early as this year. The technology, which stamps chip designs onto silicon wafers rather than using more complex light-based etching like market leader ASML's systems, could allow Canon to undercut rivals and democratize leading-edge chip production. "We would like to start shipping this year or next year...while the market is hot. It is a very unique technology that will enable cutting-edge chips to be made simply and at a low cost," said Hiroaki Takeishi, head of Canon's industrial group overseeing nanoimprint lithography technological advancement. Nanoimprint machines target a semiconductor node width of 5 nanometers, aiming to reach 2 nm eventually. Takeishi said the technology has primarily resolved previous defect rate issues, but success will depend on convincing customers that integration into existing fabrication plants is worthwhile.

There is skepticism about Canon's ability to significantly disrupt the market led by ASML's expensive but sophisticated extreme ultraviolet (EUV) lithography tools. However, if nanoimprint can increase yields to nearly 90% at lower costs, it could carve out a niche, especially with EUV supply struggling to meet surging demand. Canon's NIL machines are supposedly 40% the cost of ASML machinery, while operating with up to 90% lower power draw. Initially focusing on 3D NAND memory chips rather than complex processors, Canon must contend with export controls limiting sales to China. But with few options left, Takeishi said Canon will "pay careful attention" to sanctions risks. If successfully deployed commercially after 15+ years in development, Canon's nanoimprint technology could shift the competitive landscape by enabling new players to manufacture leading-edge semiconductors at dramatically lower costs. But it remains to be seen whether the new machines' defect rates, integration challenges, and geopolitical headwinds will allow Canon to disrupt the chipmaking giants it aims to compete with significantly.

Today, The Khronos Group, an open consortium of industry-leading companies creating advanced interoperability standards, announced the latest roadmap milestone for Vulkan, the cross-platform 3D graphics and compute API. The Vulkan roadmap targets the "immersive graphics" market, made up of mid- to high-end smartphones, tablets, laptops, consoles, and desktop devices. The Vulkan Roadmap 2024 milestone captures a set of capabilities that are expected to be supported in new products for that market, beginning in 2024. The roadmap specification provides a significant increase in functionality for the targeted devices and sets the evolutionary direction of the API, including both new hardware capabilities and improvements to the programming model for Vulkan developers.

Vulkan Roadmap 2024 is the second milestone release on the Vulkan Roadmap. Products that support it must be Vulkan 1.3 conformant and support the extensions and capabilities defined in both the 2022 and 2024 Roadmap specifications. Vulkan roadmap specifications use the Vulkan Profile mechanism to help developers build portable Vulkan applications; roadmap requirements are expressed in machine-readable JSON files, and tooling in the Vulkan SDK auto-generates code that makes it easy for developers to query for and enable profile support in their applications.

Paradox Interactive and Double Eleven have announced Prison Architect 2, the 3D successor to their prison management simulator. The game offers deeper simulation, greater player control, an inhabitant behavior system and creative options to define the next generation of management gameplay. Prison Architect 2 launches on March 26 on Steam, Xbox Series X|S, and PlayStation 5 for a suggested retail price of $39.99 / £34.99 / €39.99. Enterprising Architects can pre-order Prison Architect 2 on PC today.

Prison Architect 2 offers advanced simulation systems, enabling players to construct intricate compounds with a high degree of creative freedom in a 3D environment. From building elaborate structures to managing inmates' needs while maintaining the facility's financial stability, Prison Architect 2 expands gameplay and creative tools across the board, for an engaging sandbox experience. The game also introduces a connection system between the prisoners, who will make friends or enemies with each other, impacting who they will hang out, partner or fight with. Prison Architect 2 brings prison construction and management gameplay to a new level by entering the third dimension and bringing deeper simulation than ever before.

During the 69th annual IEEE International Electron Devices Meeting (IEDM), Intel demonstrated some of its latest transistor design and manufacturing advancements. The first one in line is the 3D integration of transistors. According to Intel, the company has successfully stacked complementary field effect transistors (CFET) at a scaled gate pitch down to 60 nm. With CFETs promising thinner gate channels, the 3D stacked CFET would allow for higher density by going vertically and horizontally. Intel's 7 node has a 54 nm gate pitch, meaning CFETs are already close to matching production-ready nodes. With more time and development, we expect to see 3D stacked CFETs in the production runs in the coming years.

Next, Intel has demonstrated RibbonFET technology, a novel approach that is the first new transistor architecture since the introduction of FinFET in 2012. Using ribbon-shaped channels surrounded by the gate, these transistors allow for better control and higher drive current at all voltage levels. This allows faster transistor switching speeds, which later lead to higher frequency and performance. The width of these nanoribbon channels can be modulated depending on the application, where low-power mobile applications use less current, making the channels thinner, and high-performance applications require more current, making the channels wider. One stack of nanoribbons can achieve the same drive current as multiple fins found in FinFET but at a smaller footprint.

Chinese memory maker Yangtze Memory Technology Corp (YMTC) is allegedly preparing its next-generation Xtacking 4.0 3D NAND flash architecture for next-generation memory chips. According to the documentation obtained by Tom's Hardware, YMTC has developed two SKUs based on the upgraded Xtacking 4.0: X4-9060, a 128-layer three-bit-per-cell (TLC) 3D NAND, and the X4-9070, a 232-layer TLC 3D NAND. By using string stacking on both of these SKUs, YMTC plans to make the 3D NAND work by incorporating arrays with 64 and 116 active layers stacked on top of each other. This way, the export regulation rules from the US government are met, and the company can use the tools that are not under the sanction list.

While YMTC has yet to fully disclose the specific advantages of the Xtacking 4.0 technology, the industry anticipates significant enhancements in data transfer speeds and storage density. These improvements are expected to stem from increased plane counts for optimized parallel processing, refined bit/word line configurations to minimize latency, and the development of modified chip variants to boost production yields. When YMTC announced Xtacking 3.0, the company offered 128-layer TLC and 232-layer four-bit-per-cell (QLC) variants and was the first company to achieve 200+ layer count in the 3D NAND space. The Xtacking 3.0 architecture incorporates string stacking and hybrid bonding techniques and uses a mature process node for the chip's CMOS underlayer. We have to wait for the final Xtacking 4.0 details when YMTC's officially launches the SKUs.

TYAN, an industry leader in server platform design and a subsidiary of MiTAC Computing Technology Corporation, debuts its new server line-up for 4th Gen AMD EPYC & AMD Ryzen Processors at SC23, Booth #1917, in the Colorado Convention Center, Denver, CO, November 13-16.

AMD EPYC 9004 processor features leadership performance and is optimized for a wide range of HPC, cloud-native computing and Generative AI workloads
TYAN offers server platforms supporting the AMD EPYC 9004 processors that provide up to 128 Zen 4C cores and 256 MB of L3 Cache for dynamic cloud-native applications with high performance, density, energy efficiency, and compatibility.

3Dconnexion, a leader in innovative input devices for professionals, is thrilled to announce the launch of the highly anticipated SpaceMouse Pro Wireless Bluetooth Edition. Purpose-built for engineers, 3D artists and architects, the new SpaceMouse Pro Wireless delivers a seamless experience centered on sustainability and meeting the evolving needs of professionals worldwide.

The SpaceMouse Pro Wireless Bluetooth Edition embodies 3Dconnexion's commitment to excellence and environmental responsibility, adding new features to the ones that professionals have been trusting and relying on for years.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced that the Rambus HBM3 Memory Controller IP now delivers up to 9.6 Gigabits per second (Gbps) performance supporting the continued evolution of the HBM3 standard. With a 50% increase over the HBM3 Gen 1 data rate of 6.4 Gbps, the Rambus HBM3 Memory Controller can enable a total memory throughput of over 1.2 Terabytes per second (TB/s) for training of recommender systems, generative AI and other demanding data center workloads.

"HBM3 is the memory of choice for AI/ML training, with large language models requiring the constant advancement of high-performance memory technologies," said Neeraj Paliwal, general manager of Silicon IP at Rambus. "Thanks to Rambus innovation and engineering excellence, we're delivering the industry's leading-edge performance of 9.6 Gbps in our HBM3 Memory Controller IP."

Zero ASIC, a semiconductor startup, came out of stealth today to announce early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

• 3D chiplet composability enabling billions of new silicon products
• Fully automated no-code chiplet-based chip design
• Zero install interactive RTL-based chip emulation
• Roadmap to 100X reduction in chip development costs

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," said Andreas Olofsson, CEO and founder of Zero ASIC. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

According to the editorial blog post published on the Samsung blog by SangJoon Hwang, Executive Vice President and Head of the DRAM Product & Technology Team at Samsung Electronics, we have information that High-Bandwidth Memory 4 (HBM4) is coming in 2025. In the recent timeline of HBM development, we saw the first appearance of HBM memory in 2015 with the AMD Radeon R9 Fury X. The second-generation HBM2 appeared with NVIDIA Tesla P100 in 2016, and the third-generation HBM3 saw the light of the day with NVIDIA Hopper GH100 GPU in 2022. Currently, Samsung has developed 9.8 Gbps HBM3E memory, which will start sampling to customers soon.

However, Samsung is more ambitious with development timelines this time, and the company expects to announce HBM4 in 2025, possibly with commercial products in the same calendar year. Interestingly, the HBM4 memory will have some technology optimized for high thermal properties, such as non-conductive film (NCF) assembly and hybrid copper bonding (HCB). The NCF is a polymer layer that enhances the stability of micro bumps and TSVs in the chip, so memory solder bump dies are protected from shock. Hybrid copper bonding is an advanced semiconductor packaging method that creates direct copper-to-copper connections between semiconductor components, enabling high-density, 3D-like packaging. It offers high I/O density, enhanced bandwidth, and improved power efficiency. It uses a copper layer as a conductor and oxide insulator instead of regular micro bumps to increase the connection density needed for HBM-like structures.

Ever since the creation of A64FX for the Fugaku supercomputer, Fujitsu has been plotting the development of next-generation CPU design for accelerating AI and general-purpose HPC workloads in the data center. Codenamed Monaka, the CPU is the latest creation for TSMC's 2 nm semiconductor manufacturing node. Based on Armv9-A ISA, the CPU will feature up to 150 cores with Scalable Vector Extensions 2 (SVE2), so it can process a wide variety of vector data sets in parallel. Using a 3D chiplet design, the 150 cores will be split into different dies and placed alongside SRAM and I/O controller. The current width of the SVE2 implementation is unknown.

The CPU is designed to support DDR5 memory and PCIe 6.0 connection for attaching storage and other accelerators. To bring cache coherency among application-specific accelerators, CXL 3.0 is present as well. Interestingly, Monaka is planned to arrive in FY2027, which starts in 2026 on January 1st. The CPU will supposedly use air cooling, meaning the design aims for power efficiency. Additionally, it is essential to note that Monaka is not a processor that will power the post-Fugaku supercomputer. The post-Fugaku supercomputer will use post-Monaka design, likely iterating on the design principles that Monaka uses and refining them for the launch of the post-Fugaku supercomputer scheduled for 2030. Below are the slides from Fujitsu's presentation, in Japenese, which highlight the design goals of the CPU.