GIGABYTE Technology,, an industry leader in high-performance servers and workstations, today announced the launch of the GIGABYTE G242-Z11 with PCIe 4.0, which adds to an already extensive line of G242 series servers, designed for AI, deep learning, data analytics, and scientific computing. High-speed interfaces such as Ethernet, Infiniband, and PCI Express rely on fast data transfer, and PCIe 3.0 can pose a bottleneck in some servers. With the expansion of the AMD EPYC family of processors comes PCIe Gen 4.0, which is valuable to servers so as not to bottleneck high bandwidth applications. The 2nd Gen AMD EPYC 7002 processors have added PCIe Gen 4.0, and GIGABYTE has included an ever-evolving line of servers to accommodate the latest technology.

The G242-Z11 caters to the capabilities of 2nd Gen AMD EPYC 7002 series processors. The G242-Z11 is built around a single AMD EPYC processor, and this even includes the new 280 W 64-core (128 threads) AMD EPYC 7H12. Besides a high core count, the 7002 series has 128 PCIe lanes and natively supports PCIe Gen 4.0. It offers double the speed and bandwidth when compared to PCIe 3.0. Having PCIe 4.0 allows for 16GT/s per lane and a total bandwidth of 64 GB/s. As far as memory support, the G242-Z11 has support for 8-channel DDR4 with room for up to 8 DIMMs. In this 1 DIMM per channel configuration, it can support up to 2 TB of memory and speeds up to 3200 MHz.

Chenbro has launched the RB23708, a Level 6, 2U rackmount server barebone designed for mission-critical, storage-focused applications in Data Center and HPC Enterprise. The RB23708 is pre-integrated with an Intel Server Board S2600WFTR that supports up to two 2nd Generation Intel Xeon Scalable "Cascade Lake" Processors.

The RB23708 is an easy-to-use barebones server solution that pre-integrates a 2-socket Intel Server Board to ensure a flexible, scalable design with mission-critical reliability. Notably, it offers Apache Pass, IPMI 2.0 & Redfish compliance, and includes Intel RSTe/Intel VROC options, providing an ideal solution for hosting Video, IMS, SaaS and similar storage-focused applications.

Asetek today announced a collaboration with Hewlett Packard Enterprise (HPE) to deliver its premium data center liquid cooling solutions in HPE Apollo Systems, which are high-performing and density-optimized to target high-performance computing (HPC) and Artificial Intelligence (AI) needs. The integration enables deployment of high wattage processors in high density configurations to support compute-intense workloads.

When developing its next-generation HPC server solutions, HPE worked closely with Asetek to define a plug and play HPC system that is integrated, installed, and serviced by HPE that serves as the ideal complement to HPE's Gen10 Plus platform. With the resulting solution, HPE is able to maximize processor and interconnect performance by efficiently cooling high density computing clusters. HPE will be deploying these DLC systems, which support warm water cooling, this calendar year.

Today, The Khronos Group, an open consortium of industry-leading companies creating graphics and compute interoperability standards, announced its SYCL 2020 Provisional Specification, for which Intel has made significant contributions through new programming abstractions. These new capabilities accelerate heterogeneous parallel programming for high-performance computing (HPC), machine learning and compute-intensive applications.

"The SYCL 2020 Provisional Specification marks a significant milestone helping improve time-to-performance in programming heterogeneous computing systems through more productive and familiar C++ programming constructs," said Jeff McVeigh, vice president of Datacenter XPU Products and Solutions at Intel Corporation. "Through active collaboration with The Khronos Group, the new specification includes significant features pioneered in oneAPI's Data Parallel C++, such as unified shared memory, group algorithms and sub-groups that were up-streamed to SYCL 2020. Moving forward, Intel's oneAPI toolkits, which include the SYCL-based Intel oneAPI DPC++ Compiler, will deliver productivity and performance for open, cross-architecture programming."

Western Digital today announced new solutions that provide the foundation for next-generation data infrastructures designed around Ultrastar NVMe SSDs and supercharged by NVMe-oF. Building upon the company's innovative design and integration capabilities - from NAND Flash to storage platforms - the new dual-port, performance Ultrastar DC SN840 NVMe SSDs and in-house RapidFlex NVMe-oF controllers are standalone solutions that combine to create the new OpenFlex Data24 NVMe-oF Storage Platform, a new shared storage JBOF (Just a Bunch of Flash) enclosure that extends the value of NVMe to multiple hosts over a low-latency Ethernet fabric network. These new solutions further expand Western Digital's data center portfolio to help customers transition to higher efficiency NVMe SSDs and more advanced shared storage architectures to meet the evolving demands of performance-driven applications and workloads.

In today's global digital economy, microseconds count. As hyperscale cloud and enterprise data centers constantly work to remove bottlenecks to ensure uncompromised performance and availability of essential applications, while also keeping pace with unprecedented data growth, customer adoption of NVMe and NVMe-oF solutions continues to accelerate. Industry analyst firm IDC expects hyperscalers, OEMs and end-user IT organizations to continue to transition away from legacy SATA and SAS interfaces, with NVMe on track to reach more than 55 percent of total enterprise SSD units shipped in 2020 and grow at a 2018-2023 CAGR of 38 percent.

ASUSTek, the leading IT Company in server systems, server motherboards and workstations today announced the new NVIDIA A100-powered server - ESC4000A E10 to accelerate and optimize data centers for high utilization and low total cost of ownership with the PCIe Gen 4 expansions, OCP 3.0 networking, faster compute and better GPU performance. ASUS continues building a strong partnership with NVIDIA to deliver unprecedented acceleration and flexibility to power the world's highest-performing elastic data centers for AI, data analytics, and HPC applications.

ASUS ESC4000A-E10 is a 2U server powered by the AMD EPYC 7002 series processors that deliver up to 2x the performance and 4x the floating point capability in a single socket versus the previous 7001 generation. Targeted for AI, HPC and VDI applications in data center or enterprise environments which require powerful CPU cores, more GPUs support, and faster transmission speed, ESC4000A E10 focuses on delivering GPU-optimized performance with support for up to four double-deck high performance or eight single-deck GPUs including the latest NVIDIA Ampere-architecture V100, Tesla, and Quadro. This also benefits on virtualization to consolidate GPU resources in to shared pool for users to utilize resources in more efficient ways.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced the launch of 'Samsung Advanced Foundry Ecosystem (SAFE ) Cloud Design Platform (CDP)' for fabless customers, in collaboration with Rescale, a leader in high performance computing (HPC) applications in the cloud. The key highlight feature of Samsung foundry's first SAFE Cloud Design Platform is that it provides a virtual environment to design chips in the cloud. By accessing this platform through the cloud, customers can immediately start designing at anytime and anywhere.

To maximize customers' design convenience, SAFE CDP supports a very secure design condition that has verified with cloud companies. In addition, customers can utilize various Electronic Design Automation (EDA) tools offered by multiple vendors such as Ansys, Cadence, Mentor, a Siemens business and Synopsys. Gaonchips, one of Samsung Foundry's Design Solution Partners, has already tested the SAFE CDP on its 14 nm automotive project using Cadence's Innovus Implementation System and has successfully reduced its design run-time by 30 percent compared to current on-premise execution.

Mark Papermaster, chief technology officer and executive vice president of Technology and Engineering at AMD, today confirmed that CDNA is on-track for release in 2H2020 for HPC computing. The confirmation was (adequately) given during Dell's EMC High-Performance Computing Online event. This confirms that AMD is looking at a busy 2nd half of the year, with both Zen 3, RDNA 2 and CDNA product lines being pushed to market.

CDNA is AMD's next push into the highly-lucrative HPC market, and will see the company differentiating their GPU architectures through market-based product differentiation. CDNA will see raster graphics hardware, display and multimedia engines, and other associated components being removed from the chip design in a bid to recoup die area for both increased processing units as well as fixed-function tensor compute hardware. CNDA-based Radeon Instinct MI100 will be fabricated under TSMC's 7 nm node, and will be the first AMD architecture featuring shared memory pools between CPUs and GPUs via the 2nd gen Infinity Fabric, which should bring about both throughput and power consumption improvements to the platform.

Kingston Digital, Inc., the Flash memory affiliate of Kingston Technology Company, Inc., a world leader in memory products and technology solutions, today began shipping the 2 TB KC2500 M.2 NVMe PCIe SSD for desktop, workstations and high-performance computing (HPC) systems. The new, higher capacity gives customers the flexibility to keep up with increasing storage needs and improves workflow.

KC2500 combines outstanding performance with endurance using the latest Gen 3.0 x 4 controller and 96-layer 3D TLC NAND, with speeds up to 3,500 MB/s read and up to 2,900 MB/s write. The self-encrypting SSD supports a full-security suite for end-to-end data protection using AES-XTS 256-bit hardware-based encryption and allows the usage of independent software vendors with TCG Opal 2.0 security management solutions such as Symantec, McAfee, WinMagic and others. KC2500 also has built-in Microsoft eDrive support, a security storage specification for use with BitLocker.

AMD and technology partner Penguin Computing Inc., a division of SMART Global Holdings, Inc, today announced that New York University (NYU), Massachusetts Institute of Technology (MIT) and Rice University are the first universities named to receive complete AMD-powered, high-performance computing systems from the AMD HPC Fund for COVID-19 research. AMD also announced it will contribute a cloud-based system powered by AMD EPYC and AMD Radeon Instinct processors located on-site at Penguin Computing, providing remote supercomputing capabilities for selected researchers around the world. Combined, the donated systems will collectively provide researchers with more than seven petaflops of compute power that can be applied to fight COVID-19.

"High performance computing technology plays a critical role in modern viral research, deepening our understanding of how specific viruses work and ultimately accelerating the development of potential therapeutics and vaccines," said Lisa Su, president and CEO, AMD. "AMD and our technology partners are proud to provide researchers around the world with these new systems that will increase the computing capability available to fight COVID-19 and support future medical research."

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced plans to boost its foundry capacity at the company's new production line in Pyeongtaek, Korea, to meet growing global demand for cutting-edge extreme ultraviolet (EUV) solutions.

The new foundry line, which will focus on EUV-based 5 nanometer (nm) and below process technology, has just commenced construction this month and is expected to be in full operation in the second half of 2021. It will play a pivotal role as Samsung aims to expand the use of state-of-the-art process technologies across a myriad of current and next generation applications, including 5G, high-performance computing (HPC) and artificial intelligence (AI).

Atos, a global leader in digital transformation, today announces its new BullSequana X2415, the first supercomputer in Europe to integrate NVIDIA's Ampere next-generation graphics processing unit architecture, the NVIDIA A100 Tensor Core GPU. This new supercomputer blade will deliver unprecedented computing power to boost application performance for HPC and AI workloads, tackling the challenges of the exascale era. The BullSequana X2415 blade will increase computing power by more than 2x and optimize energy consumption thanks to Atos' 100% highly efficient water-cooled patented DLC (Direct Liquid Cooling) solution, which uses warm water to cool the machine.

Forschungszentrum Jülich will integrate this new blade into its booster module, extending its existing JUWELS BullSequana supercomputer, making it the first system worldwide the use this new technology. The JUWELS Booster will provide researchers across Europe with significantly increased computational resources. Some of the projects it will fuel are the European Commission's Human Brain Project and the Jülich Laboratories of "Climate Science" and "Molecular Systems". Once fully deployed this summer the upgraded supercomputing system, operated under ParTec's software ParaStation Modulo, is expected to provide a computational peak performance of more than 70 Petaflops/s making it the most powerful supercomputer in Europe and a showcase for European exascale architecture.

NVIDIA today launched the NVIDIA Mellanox ConnectX -6 Lx SmartNIC—a highly secure and efficient 25/50 gigabit per second (Gb/s) Ethernet smart network interface controller (SmartNIC)—to meet surging growth in enterprise and cloud scale-out workloads.

ConnectX-6 Lx, the 11th generation product in the ConnectX family, is designed to meet the needs of modern data centers, where 25 Gb/s connections are becoming standard for handling demanding workflows, such as enterprise applications, AI and real-time analytics. The new SmartNIC extends accelerated computing by leveraging software-defined, hardware-accelerated engines to offload more security and network processing from CPUs.

AMD today announced its Radeon Pro VII professional graphics card targeting 3D artists, engineering professionals, broadcast media professionals, and HPC researchers. The card is based on AMD's "Vega 20" multi-chip module that incorporates a 7 nm (TSMC N7) GPU die, along with a 4096-bit wide HBM2 memory interface, and four memory stacks adding up to 16 GB of video memory. The GPU die is configured with 3,840 stream processors across 60 compute units, 240 TMUs, and 64 ROPs. The card is built in a workstation-optimized add-on card form-factor (rear-facing power connectors and lateral-blower cooling solution).

What separates the Radeon Pro VII from last year's Radeon VII is full double precision floating point support, which is 1:2 FP32 throughput compared to the Radeon VII, which is locked to 1:4 FP32. Specifically, the Radeon Pro VII offers 6.55 TFLOPs double-precision floating point performance (vs. 3.36 TFLOPs on the Radeon VII). Another major difference is the physical Infinity Fabric bridge interface, which lets you pair up to two of these cards in a multi-GPU setup to double the memory capacity, to 32 GB. Each GPU has two Infinity Fabric links, running at 1333 MHz, with a per-direction bandwidth of 42 GB/s. This brings the total bidirectional bandwidth to a whopping 168 GB/s—more than twice the PCIe 4.0 x16 limit of 64 GB/s.

Power Logic, a graphics card cooling solution OEM, in an interview with Taiwan tech industry observer DigiTimes, commented that it expects graphics card shipments to rise in the second half of 2020, on the backs of new product announcements from both NVIDIA and AMD, as well as HPC accelerators from the likes of Intel and NVIDIA. NVIDIA is expected to launch its "Ampere" based GeForce RTX 30-series graphics cards, while AMD is preparing to launch its Radeon RX 6000-series "Navi 2#" graphics cards based on the RDNA2 graphics architecture. Power Logic has apparently commenced prototyping certain cooling solutions, and is expected to begin mass-production at its Jiangxi-based plant towards the end of Q2-2020; so it could begin shipping coolers to graphics card manufacturers in the following quarters.

TSMC has reportedly secured orders from NVIDIA for chips based on its 7 nm and 5 nm silicon fabrication nodes, sources tell DigiTimes. If true, it could confirm rumors of NVIDIA splitting its next-generation GPU manufacturing between TSMC and Samsung. The Korean semiconductor giant is commencing 5 nm EUV mass production within Q2-2020, and NVIDIA is expected to be one of its customers. NVIDIA is expected to shed light on its next-gen graphics architecture at the GTC 2020 online event held later this month. With its "Turing" architecture approaching six quarters of market presence, it's likely that the decks are being cleared for a new architecture not just in HPC/AI compute product segment, but also GeForce and Quadro consumer graphics cards. Splitting manufacturing between TSMC and Samsung would help NVIDIA disperse any yield issue arriving from either foundry's EUV node, and give it greater bargaining power with both.

Silicon Valley startup Tachyum, founded in 2016, is ready with its crowning product, the Tachyum Prodigy. The startup recently received an investment from the Slovak government in hopes of job-creation in the country. The Prodigy is what its makers call "a universal processor," which "outperforms the fastest Xeon at 10X lower power." The company won't mention what machine architecture it uses (whether it's Arm or MIPS, or its own architecture). Its data-sheet is otherwise full of specs that scream at you.

To begin with, its top trim, the Prodigy T16128, packs 128 cores on a single package, complete with 64-bit address space, 512-bit vector extensions, matrix multiplication fixed-function hardware that accelerate AI/ML, and 4 IPC at up to 4.00 GHz core clock. Tachyum began the processor's software-side support, with an FPGA emulator in December 2019 (so you can emulate the processor on an FPGA and begin developing for it), C/C++ and Fortran compilers; debuggers and profilers, tensorflow compilers, and a Linux distribution that's optimized it. The I/O capabilities of this chip are something else.

The National Energy Research Scientific Computing Center (NERSC), the mission high-performance computing facility for the U.S. Department of Energy's Office of Science, has moved another step closer to making Perlmutter - its next-generation GPU-accelerated supercomputer - available to the science community in 2020.

In mid-April, NERSC finalized its contract with Cray - which was acquired by Hewlett Packard Enterprise (HPE) in September 2019 - for the new system, a Cray Shasta supercomputer that will feature 24 cabinets and provide 3-4 times the capability of NERSC's current supercomputer, Cori. Perlmutter will be deployed at NERSC in two phases: the first set of 12 cabinets, featuring GPU-accelerated nodes, will arrive in late 2020; the second set, featuring CPU-only nodes, will arrive in mid-2021. A 35-petabyte all-flash Lustre-based file system using HPE's ClusterStor E1000 hardware will also be deployed in late 2020.

Cloud data centers are evolving to an architecture that is accelerated, disaggregated and software-defined to meet the exponential growth in AI and high performance computing. To build these modern data centers, HPC and networking hardware and software must go hand in hand. NVIDIA provides the leading accelerated computing platform. Mellanox is the high-performance networking leader, now part of NVIDIA in a combination described in our founder and CEO's welcome letter.

Today we announce our plan to acquire Cumulus Networks, bolstering our networking software capabilities. The combination enables the new era of the accelerated, software-defined data center. With Cumulus, NVIDIA can innovate and optimize across the entire networking stack from chips and systems to software including analytics like Cumulus NetQ, delivering great performance and value to customers. This open networking platform is extensible and allows enterprise and cloud-scale data centers full control over their operations.

NVIDIA will give its DGX line of pre-built deep-learning research workstations its next major update in the form of the DGX A100. This system will likely pack number of the company's upcoming Tesla A100 scalar compute accelerators based on its next-generation "Ampere" architecture and "GA100" silicon. The A100 came to light though fresh trademark applications by the company. As for specs and numbers, we don't know yet. The "Volta" based DGX-2 has up to sixteen "GV100" based Tesla boards adding up to 81,920 CUDA cores and 512 GB of HBM2 memory. One can expect NVIDIA to beat this count. The leading "Ampere" part could be HPC-focused, featuring a large CUDA-, and tensor core count, besides exotic memory such as HBM2E. We should learn more about it at the upcoming GTC 2020 online event.

The Intel Graphics Twitter account was on fire today, because they posted an update on the development of the Xe graphics processor, mentioning that samples are ready and packed up in quite an interesting package. The processor in question was discovered to be a Xe-HP GPU variant with an estimated die size of 3700 mm², which means we sure are talking about a multi-chip package here. How we concluded that it is the Xe-HP GPU, is by words of Raja Koduri, senior vice president, chief architect, general manager for Architecture, Graphics, and Software at Intel. He made a tweet, which was later deleted, that says this processor is a "baap of all", meaning "big daddy of them all" when translated from Hindi.

Mr. Koduri previously tweeted a photo of the Intel Graphics team at India, which has been working on the same "baap of all" GPU, which suggests this is a Xe-HP chip. It seems that this is not the version of the GPU made for HPC workloads (this is reserved for the Xe-HPC GPU), this model could be a direct competitor to offers like NVIDIA Quadro or AMD Radeon Pro. We can't wait to learn more about Intel's Xe GPUs, so stay tuned. Mr. Koduri has confirmed that this GPU will be used only for Data Centric applications as it is needed to "keep up with the data we are generating". He has also added that the focus for gaming GPUs is to start off with better integrated GPUs and low power chips above that, that could reach millions of users. That will be a good beginning as that will enable software preparation for possible high-performance GPUs in future.

Update May 2: changed "father" to "big daddy", as that's the better translation for "baap".
Update 2, May 3rd: The GPU is confirmed to be a Data Center component.

Today, The Khronos Group, an open consortium of industry-leading companies creating advanced interoperability standards, publicly releases the OpenCL 3.0 Provisional Specifications. OpenCL 3.0 realigns the OpenCL roadmap to enable developer-requested functionality to be broadly deployed by hardware vendors, and it significantly increases deployment flexibility by empowering conformant OpenCL implementations to focus on functionality relevant to their target markets. OpenCL 3.0 also integrates subgroup functionality into the core specification, ships with a new OpenCL C 3.0 language specification, uses a new unified specification format, and introduces extensions for asynchronous data copies to enable a new class of embedded processors. The provisional OpenCL 3.0 specifications enable the developer community to provide feedback on GitHub before the specifications and conformance tests are finalized.

SiPearl, the company that is designing the high-performance, low-power microprocessor for the European exascale supercomputer, has signed a major technological licensing agreement with Arm, the global semiconductor IP provider. The agreement will enable SiPearl to benefit from the high-performance, secure, and scalable next-generation Arm Neoverse platform, codenamed ''Zeusʺ, as well as leverage the robust software and hardware Arm ecosystem.

Taking advantage of the Arm "Zeus" platform, including Arm's POP IP, on advanced FinFET technologyenables SiPearl to accelerate its design and ensure outstanding reliability for a very high-end offering,in terms of both computing power and energy efficiency, and be ready to launch its first generation of microprocessors in 2022.

AMD on April 15 updated its COVID-19 response strategy to include a sizable donation of enterprise hardware from its inventory towards COVID-19 vaccine research. The company is giving away $15 million worth HPCs cloud computing nodes powered by EPYC enterprise processors and Radeon Instinct scalar compute accelerators to key research institutions at the forefront of vaccine research for COVID-19. AMD says that these systems will be of a turnkey nature, so they could be quickly deployed and put to use. The company invites any institution conducting COVID-19 related research to contact them for access to the node.

Making the announcement, CEO Dr. Lisa Su writes: "AMD is announcing today a COVID-19 HPC fund to provide research institutions with computing resources to accelerate medical research on COVID-19 and other diseases. The fund will include an initial donation of $15 million of high-performance systems powered by AMD EPYC CPUs and AMD Radeon Instinct GPUs to key research institutions. To ease the implementation and speed the useful impact from these donations, we are working with our HPC system provider partners to provide ready-to-install HPC nodes. Research institutions should contact AMD at COVID-19HPC[at]amd[dot]com to submit proposals for access to these nodes."

AMD and NVIDIA are the latest computing giants to join the HPC COVID-19 Consortium, they join the likes of Google, Amazon, Microsoft along with the US Federal Government and Academic Institutions in support of COVID-19 research. This announcement brings the combined power of the cluster to 402 petaflops which trails behind the community driven Folding@Home project which holds the record at 1,500 petaflops but is still more powerful than any one supercomputer.

Researchers can apply to the HPC COVID-19 Consortium for compute resources in the fight against COVID-19.