Another quarter, another record breaking earnings report by TSMC, but it seems like the company has released that things are set to slow down sooner than initially expected and the company is hitting the brakes on some of its expansion projects. The company saw a 79.7 percent increase in profits compared to last year, with a profit of US$8.8 billion and a revenue of somewhere between US$19.9 to US$ 20.7 billion for the third quarter, which is a 47.9 percent bump compared to last year. TSMC's 5 nm nodes were the source for 28 percent of the revenues, followed by 26 percent for 7 nm nodes, 12 percent for 16 nm and 10 percent for 28 nm, with remaining nodes at 40 nm and larger making up for the remainder of the revenue. By platform, smartphone chips made up 41 percent, followed by High Performance Computing at 39 percent, IoT at 10 percent and automotive at five percent.

TSMC said it will cut back its CAPEX budget by around US$4 billion, to US$36 billion, compared to the earlier stated US$40 billion budget the company had set aside for expanding its fabs. Part of the reason for this is that TSMC is already seeing weaker demand for products manufactured using its N7 and N6 nodes, as the N7 node was meant to be a key part of the new fab in Kaohsiung in southern Taiwan. TSMC is expecting to start production on its first N3 node later this quarter and is expecting the capacity to be fully utilised for all of 2023. Supply is said to be exceeding demand, which TSMC said is partially to blame on tooling delivery issues. TSMC is expecting next year's revenue for its N3 node to be higher than its N5 node in 2020, although the revenue is said to be in the single digit percentage range. The N3E node is said to start production sometime in the second half of next year, or about a quarter earlier than expected. The N2 node isn't due to start production until 2025, but TSMC is already having very high customer engagement, so it doesn't look like TSMC is likely to suffer from a lack of business in the foreseeable future, as long as the company keeps delivering new nodes as planned.

With AMD announcing an October 2022 debut of its mid-range Socket AM5 motherboard chipset, the AMD B650E and B650; manufacturers appear to be ready with a fairly broad selection of products targeting various price-points. The B650E and B650 are expected to have a lighter I/O feature-set than the X670E/X670, and will enable manufacturers to sell motherboards at prices starting at $125. Two of the leading manufacturers, ASUS and ASRock, are ready with their product lists.

The initial ASUS motherboard lineup for the AMD B650E and B650 chipsets include just one product in the mainline Prime series, as many as four from the TUF Gaming series, and two from the ROG Strix series. From these, only one is based on the B650E (meaning, it gets a PCI-Express 5.0 x16 slot besides the M.2 Gen 5 slot). The others are based on the vanilla B650 (PCI-Express 4.0 x16 slot besides M.2 Gen 5 slots). None of the boards has more than 4 SATA 6 Gbps ports. The board to watch out for will be the ROG Strix B650E-E Gaming WiFi, as it could bring several high-end features into the mid-range, and if previous generations of AMD chipset are anything to go by, the B650/E retains CPU overclocking support.

A new quarter and another forecast shattering revenue report from TSMC, as the company beat analysts' forecasts by over US$658 million, with a total revenue for the quarter of US$17.6 billion and a net income of almost US$7.26 billion. That's an increase in net income of 45.1 percent or 35.5 percent in sales. Although the monetary figures might be interesting to some, far more interesting details were also shared, such as production updates about future nodes. As a followup on yesterday's news post about 3 nanometer nodes, the N3 node is officially on track for mass production in the second half of this year. TSMC says that customer engagement is stronger than at the start of its N7 and N7 nodes, with HPC and smartphone chip makers lining up to get onboard. The N3E node is, as reported yesterday, expected to enter mass production in the second half of 2023, or a year after N3. Finally, the N2 node is expected in 2025 and won't adhere to TSMC's two year process technology cadence.

Breaking down the revenue by nodes, N7 has taken back the lead over N5, as N7 accounted for 30 percent of TSMC's Q1 revenues up from 27 percent last quarter, but down from 35 percent in the previous year. N5 sits at 20 percent, which is down from 23 percent in the previous quarter, but up from 14 percent a year ago. The 16 and 28 nm nodes still hold on to 25 percent of TSMC's revenue, which is the same as a year ago and up slightly from the previous quarter. Remaining nodes are unchanged from last quarter.

Here is the first picture of a next-generation AMD EPYC "Genoa" processor with its integrated heatspreader (IHS) removed. This is also possibly the first picture of a "Zen 4" CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. The "Zen 4" CCDs, built on the TSMC N5 (5 nm EUV) process, look visibly similar in size to the "Zen 3" CCDs built on the N7 (7 nm) process, which means the CCD's transistor count could be significantly higher, given the transistor-density gained from the 5 nm node. Besides more number-crunching machinery on the CPU core, we're hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the "Zen" microarchitecture.

Each "Zen 4" CCD is reported to be about 8 mm² smaller in die-area than the "Zen 3" CCD, or about 10% smaller. What's interesting, though, is that the sIOD (server I/O die) is smaller in size, too, estimated to measure 397 mm², compared to the 416 mm² of the "Rome" and "Milan" sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 nm), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 nm). Supporting this theory is the fact that the "Genoa" sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Infinity Fabric over package) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 nm, for the sIOD. AMD is expected to debut the EPYC "Genoa" enterprise processors in the second half of 2022.

During the International Solid-State Circuits Conference (ISSCC) 2022, Intel gave us a more significant look at its upcoming Ponte Vecchio HPC accelerator and how it operates. So far, Intel convinced us that the company created Ponte Vecchio out of 47 tiles glued together in one package. However, the ISSCC presentation shows that the accelerator is structured rather interestingly. There are 63 tiles in total, where 16 are reserved for compute, eight are used for RAMBO cache, two are Foveros base tiles, two represent Xe-Link tiles, eight are HBM2E tiles, and EMIB connection takes up 11 tiles. This totals for about 47 tiles. However, an additional 16 thermal tiles used in Ponte Vecchio regulate the massive TDP output of this accelerator.

What is interesting is that Intel gave away details of the RAMBO cache. This novel SRAM technology uses four banks of 3.75 MB groups total of 15 MB per tile. They are connected to the fabric at 1.3 TB/s connection per chip. In contrast, compute tiles are connected at 2.6 TB/s speeds to the chip fabric. With eight RAMBO cache tiles, we get an additional 120 MB SRAM present. The base tile is a 646 mm² die manufactured in Intel 7 semiconductor process and contains 17 layers. It includes a memory controller, the Fully Integrated Voltage Regulators (FIVR), power management, 16-lane PCIe 5.0 connection, and CXL interface. The entire area of Ponte Vecchio is rather impressive, as 47 active tiles take up 2,330 mm², whereas when we include thermal dies, the total area jumps to 3,100 mm². And, of course, the entire package is much larger at 4,844 mm², connected to the system with 4,468 pins.

AMD is allegedly preparing to announce the Radeon RX 6000S mobile graphics card based on a refreshed RDNA 2 architecture. The new card will be manufactured on TSMC's N6 process which offers an 18% logic density improvement over the N7 process currently used for RDNA 2 products resulting in increased efficiency or performance. The switch to the IP compatible N6 node should also improve yields and shorten production cycles allowing AMD to remain competitive with new cards from NVIDIA and Intel. We have limited information on this alleged card except that it will likely be announced in early 2022 at CES and that AMD may also release discrete RX 6000S series desktop graphics cards.

With ever increasing computational needs from TV SoCs, as we're moving towards higher resolutions and refresh rates, MediaTek is getting ready for the next generation of 8K TVs with its new Pentonic 2000 SoC. This is the world's first TV SoC to support the new H.266 video codec standard, which is an evolution of the H.265 intended for 8K content.

The Pentonic 2000 is fabbed using TSMC's N7 node and it's the first commercial TV SoC to be made on this manufacturing process according to MediaTek. The SoC supports 8K resolution content at up to 120 Hz with MEMC (Motion Estimation, Motion Compensation) and has an integrated AI engine to help improve scaling from lower resolutions. MediaTek also claims that the Pentonic 2000 features the "industry's most powerful CPU and GPU" in a smart TV SoC, without giving away any actual details, although it the SoC does support UFS 3.1 storage, which suggests that we're looking at a recent Arm Cortex-A7x based SoC at the very least.

The lineup of 600-Series motherboards planned by ASRock and NZXT for the upcoming 12th Generation Intel Core Series of processors has recently been published by VideoCardz. While NZXT has only two high-end Z590 motherboards listed with them being the N5-Z69XT, and the N7-Z69XT, ASRock has 36 listed across all the Z690, H670, B660, and H610 chipsets. The Z690 chipset will serve as the flagship platform for high-performance and overclocking while the H670 and B660 will take the mid-range and the H610 for entry-level boards. The list does not contain any Taichi, Aqua, or OC Formula series boards from ASRock as those may not be ready for day-one release or are still under active development.

ASRock will offer several of their motherboards in two variants with one offering integrated WiFi 6E networking, they also have an ITX option for each chipset. Intel is expected to announce their 12th Generation Core Series processors and Z690 chipset in late 2021 with the remaining chipsets to be announced at CES 2022. The entire list of motherboards from the two companies can be found below.

NZXT, a leading designer of computer hardware, software, and services for the PC gaming community, today announces the release of the NZXT N7 Z590 motherboard, their latest Intel-based ATX motherboard with both the features and seamless aesthetic that builders love.

The NZXT N7 Z590 brings the sleek design and simplified building experience to Intel's newest chipset, supporting Intel's 11th generation Rocket Lake CPUs, PCIe gen 4, and the latest wireless connectivity standards which includes Wi-Fi 6e and Bluetooth V5.1. Community feedback was the inspiration for adding additional rear I/O, as well as improved thermal performance with more power phases and layers to the printed circuit board.

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced immediate availability of Cadence IP supporting the PCI Express (PCIe ) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence's PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market.

The Cadence IP for PCIe 5.0 architecture offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss. Leveraging Cadence's existing N7/N6 silicon validated offering, the N5 design provides a full 512GT/s (gigatransfers per second) power-optimized solution across the full range of operating conditions with a single clock lane.

It's not only graphics cards and CPUs that are best kept on the edge of manufacturing processes; in truth, one could even say that consoles have more to gain from these transitions when it comes to their manufacturers' financial outlooks. This happens because usually, consoles are subsidized by manufacturers in that their actual retail price is lower than manufacturing costs; this works as a way for console players to increase their platforms' attractiveness and user base, so they can then sell them games and subscription services, where the big bucks are actually made. We knew this already, but Microsoft's head of Xbox business development, Lori Wright confirmed it yesterday at the Apple vs Epic Games hearing. Lori Wright is quoted as answering "We don't; we sell the consoles at a loss" when asked whether Microsoft does or does not turn a profit on Xbox Series S | X hardware sales.

Considering the similarities between the Xbox Series X and PS5's SoC, it's very likely that Sony doesn't make a profit on console hardware sales either - or if it actually does, it's nothing actually meaningful. This is part of the reason why consoles are usually actually in the forefront of manufacturing processes' advancements, as it's a way for console players to quickly reduce the BoM (Bill of Materials) for their consoles. Since the specifications don't change within a console generation (discounting Pro models, which both companies have taken to launching some years into their generations), they choose to take advantage of process advancements due to the transistor density increases that allow for both lower silicon area for the SoC, and lower power consumption - which sometimes enables them to develop slim versions of their gaming consoles.

NZXT, a leading designer of computer hardware, software, and services for the PC gaming community, today announces the release of the NZXT N7 B550 motherboard, the first AMD motherboard in NZXT's N7 motherboard lineup. NZXT is expanding the N7 lineup to bring the sleek, seamless design of the N7 ATX motherboard to more gamers. The N7 B550 has optimally placed port locations, supports the latest technology like PCIe gen 4 and WiFi 6e, and gives PC builders the tools they need to create a beautifully modern build.

The N7 B550 includes key features from our RGB and Fan Controller, allowing intuitive control of four RGB lighting channels and seven fan channels through NZXT CAM. Lighting accessories from all manufacturers are supported. The metal cover is available in white or black for a seamless look that blends into the background of any NZXT H Series case for a clean aesthetic.

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

TSMC on Monday kicked off a virtual tech symposium, where it announced its new 12 nm N12e node for IoT edge devices, announced the new 3DFabric Technology, and detailed progress on its upcoming 5 nm N5 and 3 nm N3 silicon fabrication nodes. The company maintains that the N5 (5 nm) node offers the benefits of a full node uplift over its current-gen N7 (7 nm), which recently clocked over 1 billion chips shipped. The N5 node incorporates EUV lithography more extensively than N6/N7+, and in comparison to N7 offers 30% better power at the same performance, 15% more performance at the same power, and an 80% increase in logic density. The company has commenced high-volume manufacturing on this node.

2021 will see the introduction and ramp-up of the N5P node, an enhancement of the 5 nm N5 node, offering a 10% improvement in power at the same performance, or 5% increase in performance at the same power. A nodelet of the N5 family of nodes, called N4, could see risk production in Q4 2021. The N4 node is advertised as "4 nm," although the company didn't get into its iso-power/iso-performance specifics over the N5 node. The next major node for TSMC will be the 3 nm N3 node, with massive 25%-30% improvement in power at the same performance, or 10%-15% improvement in performance at same power, compared to N5. It also offers a 70% logic density gain over N5. 3DFabric technology is a new umbrella term for TSMC's CoWoS (chip on wafer on substrate), CoW (chip on wafer), and WoW (wafer on wafer) 3-D packaging innovations, with which it plans to offer packaging innovations that compete with Intel's various new 3D chip packaging technologies on the anvil.

In a bid to show off its volume production prowess and technological edge (but mostly to rub it in to rival fabs), TSMC on Thursday announced that it shipped its 1 billionth chip fabricated on its 7 nm process. If these dies were combined into one big rectangular wafer, they would cover 13 New York City blocks. TSMC's 7 nm process debuted with its N7 node, which went into volume production in April 2018, over two years ago. The fab has since mass-produced 7 nm chips for the likes of Qualcomm, Apple, and AMD, among dozens of other clients. The company now looks to monetize refinements of N7, namely the N7e and N7P (DUV refinements), while executing its crucial EUV-based N7+ node, leading up to future nodelets such as N6. Much of TSMC's growth will be propelled by 5G modems, application processors, and its pivotal role in the growth of companies such as AMD.

With its own 7 nm-class silicon fabrication node nowhere in sight for its processors, at least not until 2022-23, Intel is seeking out third-party semiconductor foundries to support its ambitious discrete GPU and scalar compute processor lineup under the Xe brand. A Taiwanese newspaper article interpreted by Chiakokhua provides a fascinating insight to the the new precious resource in the high-technology industry - allocation.

TSMC is one of these foundries, and will give Intel access to a refined 7 nm-class node, either the N7P or N7+, for some of its Xe scalar compute processors. The company could also seek out nodelets such as the N6. Trouble is, Intel will be locking horns with the likes of AMD for precious foundry allocation. NVIDIA too has secured a certain allocation of TSMC 7 nm for some of its upcoming "Ampere" GPUs. Sources tell China Times that TSMC will commence mass-production of Intel silicon as early as 2021, on either N7P, N7+, or N6. Business from Intel is timely for TSMC as it is losing orders from HiSilicon (Huawei) in wake of the prevailing geopolitical climate.

Here are some of the first pictures of the N7 Z490 motherboards by NZXT. Historically, NZXT is known to source its motherboard through OEMs such as ECS, but with great design and quality oversight, which could be the case with the Z490-based N7 board, too. Built in the ATX form-factor, the N7 Z490 draws power from a combination of 24-pin ATX, and 8+4 pin EPS power connectors, conditioning it for the CPU with a 12-phase VRM. The board is characterized by a front shroud that covers most of the business side of the PCB, and comes either in matte black or white, blending into the design scheme NZXT uses for its cases.

Expansion slots on the N7 Z490 appear to include one PCI-Express 3.0 x16, one x16 (electrical x4), and three x1 slots. Storage options include two M.2-2280 slots, each with PCI-Express 3.0 x4 wiring; and four SATA 6 Gbps ports. USB connectivity includes two 10 Gbps USB 3.1 gen 2 ports (from which one is type-C), and four 5 Gbps USB 3.1 gen 1 ports. An HDMI port provides the sole display output. Networking options include 802.11ax + Bluetooth 5 provided by an Intel AX201 WLAN card; and 2.5 GbE wired networking from a Realtek RTL8125BG controller. The onboard audio solution uses premium Realtek ALC1220 HD audio codec. There's no information on pricing or availability.

TSMC is reportedly planning a stopgap between its 5 nm-class silicon fabrication nodes, and the 3 nm-class, called N4. According to the foundry's CEO, Liu Deyin, speaking at a shareholders meeting, N4 will be a 4 nm node, and an enhancement of N5P, the company's most advanced 5 nm-class node. N4 is slated for mass-production of contracted products in 2023, and could help TSMC's customers execute their product roadmaps of the time. From the looks of it, N4 is a repeat of the N6 story: a nodelet that's an enhancement of N7+, the company's most advanced 7 nm-class node that leverages EUV lithography.

A DigiTimes premium report, interpreted by Chiakokhua, aka Retired Engineer, chronicling NVIDIA's move to contract TSMC for 7 nm and 5 nm EUV nodes for GPU manufacturing, made a startling revelation about NVIDIA's recent foundry diversification moves. Back in July 2019, a leading Korean publication confirmed NVIDIA's decision to contract Samsung for its next-generation GPU manufacturing. This was a week before AMD announced its first new-generation 7 nm products built for the TSMC N7 node, "Navi" and "Zen 2." The DigiTimes report reveals that NVIDIA underestimated the efficiency gains AMD would yield from TSMC N7.

With NVIDIA's bonhomie with Samsung underway, and Apple transitioning to TSMC N5, AMD moved in to quickly grab 7 nm-class foundry allocation and gained prominence with the Taiwanese foundry. The report also calls out a possible strategic error on NVIDIA's part. Upon realizing the efficiency gains AMD managed, NVIDIA decided to bet on TSMC again (apparently without withdrawing from its partnership with Samsung), only to find that AMD had secured a big chunk of its nodal allocation needed to support its growth in the x86 processor and discrete GPU markets. NVIDIA has hence decided to leapfrog AMD by adapting its next-generation graphics architectures to TSMC's EUV nodes, namely the N7+ and N5. The report also speaks of NVIDIA using its Samsung foundry allocation as a bargaining chip in price negotiations with TSMC, but with limited success as TSMC established its 7 nm-class industry leadership. As it stands now, NVIDIA may manufacture its 7 nm-class and 5 nm-class GPUs on both TSMC and Samsung.

With an introduction of new iPad Pro tablets, Apple has brought another new silicon to its offerings in the form of A12Z SoC. Following the previous king in tablet space, the A12X SoC, Apple has decided to update its silicon and now there is another, more advanced stepping in form of an A12Z SoC. Thanks to the report from TechInsights, their analysis has shown that the new SoC used in Apple's devices is pretty much the same compared to the A12X SoC of last year, except the GPU used. Namely, the configuration of A12X is translated into the A12Z - there are four Apple Vortex and four Apple Tempest cores for the CPU. There is a 128-bit memory bus designed for LPDDR4X memory, the same as the A12X.

What is different, however, is the GPU cluster configuration. In A12X there was a cluster filled with 7 working and one disabled A12-gen GPU core. In A12Z SoC all of the 8 GPUs present are enabled and working, and they are also of the same A12 generation. The new SoC is even built using the same N7 7 nm manufacturing process from TSMC. While we don't know the silicon stepping revision of the A12Z, there aren't any new features besides the additional GPU core.

A WikiChip analysis of TSMC's next-generation 5 nanometer N5P silicon fabrication node estimates a massive 84-87% increase in transistor densities on offer compared to the company's first commercial 7 nm-class node, the N7 (7 nm DUV). The report estimates an 87% transistor-density increase, even though TSMC's own figure is slightly modest, at 84%. TSMC N5P node is expected to commence production later this year. Its precursor, TSMC N5, began risk production earlier this year, with production on the node commencing in April or May, unless derailed by the COVID-19 pandemic. The N5P node provides transistor densities of an estimated 171.3 million transistors per mm² die area, compared to 91.2 mTr/mm² of N7. Apple is expected to be the node's biggest customer in 2020, with the company building its A14-series SoC on it.

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.

TSMC vice chairman and CEO C.C. Wei announced the company's plans for 5 nm are on track, which means High Volume manufacturing (HVM) on the node is expected to be achieved by 2Q 2020. The company has increased expenditures in ramping up its various nodes from an initially projected $10 billion to something along the lines of $14 billion - 15 billion; the company is really banking on quick uptake and design wins on its most modern process technologies - and the increased demand that follows.

TSMC's 5 nm process (N5) will use extreme ultraviolet lithography (EUVL) in many more layers than its N7+ and N6 processes, with up to 14 layers being etched in the N5 silicon compared to five and six, respectively, for its "older" N7+ and N6 processes. As the company increases capital expenditure in acquiring EUVL-capable equipment that sets up its production nodes for the market they foresee will just gobble up the chips in 2020, the company is optimistic they can achieve growth in the 5-10% number.

TSMC today announced that its seven-nanometer plus (N7+), the industry's first commercially available Extreme Ultraviolet (EUV) lithography technology, is delivering customer products to market in high volume. The N7+ process with EUV technology is built on TSMC's successful 7 nm node and paves the way for 6 nm and more advanced technologies.

The N7+ volume production is one of the fastest on record. N7+, which began volume production in the second quarter of 2019, is matching yields similar to the original N7 process that has been in volume production for more than one year.

TSMC in its quarterly earnings call expressed confidence in that most of its 7 nm (N7) process production node customers would be looking to make the transition to their 6 nm (N6) process. In fact, the company expects that node to become the biggest target for volume ordering (and thus production) amongst its customers, since the new N6 fabrication technology will bring about a sort of "backwards compatibility" with design tools and semiconductor designs that manufacturers have already invested in for its N7 node, thus allowing for cost savings for its clients.

This is despite TSMC's N6 process being able to take advantage of extreme ultraviolet lithography (EUVL) to lower manufacturing complexity. This lowering is achieved by the fact that less exposures of the silicon are required for multi-patterning - which is needed today as TSMC's N7 uses solely deep ultraviolet (DUV) lithography. Interestingly, TSMC expects other clients to pick up its N7+ manufacturing node that aren't already using their 7nm node - the need to develop new tools and lesser design compatibility between its N7 and N7+ nodes compared no N7 and N6 being the justification. TSMC's N7+ will be the first node to leverage EUV, using up to four EUVL layers, while N6 expands it up to five layers, and the upcoming N5 cranks EUVL up to fourteen (allowing for 14 layers.)