Apple and Samsung are reportedly in the fray to acquire Intel, according a spectacular rumor cited by Moore's Law is Dead. This would put the list of companies looking to acquire Intel at 3—Apple, Samsung, and Qualcomm. All three are Arm licensees, with unique characteristics. Apple currently has an Arm-based SoC hardware division that makes custom chips for all its devices, including Macs. Samsung would go on to be an overseas parent company for an American heritage company like Intel, but something like this is not unheard of when you consider examples such as Boston Dynamics being acquired by Hyundai Motors, or Westinghouse Nuclear's acquisition by Japan's Toshiba, before changing hands to Canadian Bookfield Partners. Then there's Qualcomm—the American company is having a bit of a falling out with Arm, and the prospect of owning the x86 IP should be tempting.

Intel retains large amounts of market-share in both the PC processor and server processor markets, however, the company's stock price has been on a downward trend for several quarters now, causing its valuation to drop to levels where any of the other big tech companies can afford to buy it out. The company spent close to $10 billion on a GPU architecture project spanning not just a contemporary graphics architecture to power the integrated graphics solutions of its PC processors, but also discrete gaming GPUs; and most importantly, an AI GPU architecture under the "Ponte Vecchio" project. Intel's Xe-HP AI GPU missed its performance targets or was too late to the market, leaving Intel with a gaping hole that it could only fill with a slew of cost-cutting measures. It doesn't help that Intel Foundry is losing its edge, and none of the logic tiles of Core Ultra "Arrow Lake" processor is made on an Intel foundry node.

AMD reportedly plans to incorporate glass substrates into its high-performance system-in-packages (SiPs) sometimes between 2025 and 2026. Glass substrates offer several advantages over traditional organic substrates, including superior flatness, thermal properties, and mechanical strength. These characteristics make them well-suited for advanced SiPs containing multiple chiplets, especially in data center applications where performance and durability are critical. The adoption of glass substrates aligns with the industry's broader trend towards more complex chip designs. As leading-edge process technologies become increasingly expensive and yield gains diminish, manufacturers turn to multi-chiplet designs to improve performance. AMD's current EPYC server processors already incorporate up to 13 chiplets, while its Instinct AI accelerators feature 22 pieces of silicon. A more extreme testament is Intel's Ponte Vecchio, which utilized 63 tiles in a single package.

Glass substrates could enable AMD to create even more complex designs without relying on costly interposers, potentially reducing overall production expenses. This technology could further boost the performance of AI and HPC accelerators, which are a growing market and require constant innovation. The glass substrate market is heating up, with major players like Intel, Samsung, and LG Innotek also investing heavily in this technology. Market projections suggest explosive growth, from $23 million in 2024 to $4.2 billion by 2034. Last year, Intel committed to investing up to 1.3 trillion Won (almost one billion USD) to start applying glass substrates to its processors by 2028. Everything suggests that glass substrates are the future of chip design, and we await to see first high-volume production designs.

Intel's upcoming Falcon Shores GPU is shaping up to be a powerhouse for AI and high-performance computing (HPC) workloads, but it will also be an extreme power hog. The processor, combining Gaudi and Ponte Vecchio successors into a single GPU, is expected to consume an astonishing 1500 W of power - more than even Nvidia's beefy B200 accelerator, which draws 1000 W. This immense power consumption will require advanced cooling solutions to ensure the Falcon Shores GPU operates efficiently and safely. Intel's partners may turn to liquid cooling or even full immersion liquid cooling, a technology Intel has been promoting for power-hungry data center hardware. The high power draw is the cost of the Falcon Shores GPU's formidable performance promises. Intel claims it will deliver 5x higher performance per watt and 5x more memory capacity and bandwidth compared to its Ponte Vecchio products.

Intel may need to develop proprietary hardware modules or a new Open Accelerator Module (OAM) spec to support such extreme power levels, as the current OAM 2.0 tops out around 1000 W. Slated for release in 2025, the Falcon Shores GPU will be Intel's GPU IP based on its next-gen Xe graphics architecture. It aims to be a major player in the AI accelerator market, backed by Intel's robust oneAPI software development ecosystem. While the 1500 W power consumption is sure to raise eyebrows, Intel is betting that the Falcon Shores GPU's supposedly impressive performance will make it an enticing option for AI and HPC customers willing to invest in robust cooling infrastructure. The ultra-high-end accelerator market is heating up, and the HPC accelerator market needs a Ponte Vecchio successor.

According to ServeTheHome, Intel has decided to discontinue its high-performance computing (HPC) product line, Ponte Vecchio, and shift its focus towards developing its next-generation data center GPU, codenamed Falcon Shores. This decision comes as Intel aims to streamline its operations and concentrate its resources on the most promising and competitive offerings. The Ponte Vecchio GPU, released in January of 2023, was intended to be Intel's flagship product for the HPC market, competing against the likes of NVIDIA's H100 and AMD's Instinct MI series. However, despite its impressive specifications and features, Ponte Vecchio faced significant delays and challenges in its development and production cycle. Intel's decision to abandon Ponte Vecchio is pragmatic, recognizing the intense competition and rapidly evolving landscape of the data center GPU market.

By pivoting its attention to Falcon Shores, Intel aims to deliver a more competitive and cutting-edge solution that can effectively challenge the dominance of its rivals. Falcon Shores, slated for release in 2025, is expected to leverage Intel's latest process node and architectural innovations. Currently, Intel has Gaudi 2 and Gaudi 3 accelerators for AI. However, the HPC segment is left without a clear leader in the company's product offerings. Intel's Ponte Vecchio is powering Aurora exascale supercomputer, which is the latest submission to the TOP500 supercomputer lists. This is also coming after the Rialto Bridge cancellation, which was supposed to be an HPC-focused card. In the future, the company will focus only on the Falcon Shores accelerator, which will unify HPC and AI needs for high-precision FP64 and lower-precision FP16/INT8.

During the recent IEDM conference, TSMC previewed its process roadmap for delivering next-generation chip packages packing over one trillion transistors by 2030. This aligns with similar long-term visions from Intel. Such enormous transistor counts will come through advanced 3D packaging of multiple chipsets. But TSMC also aims to push monolithic chip complexity higher, ultimately enabling 200 billion transistor designs on a single die. This requires steady enhancement of TSMC's planned N2, N2P, N1.4, and N1 nodes, which are slated to arrive between now and the end of the decade. While multi-chipset architectures are currently gaining favor, TSMC asserts both packaging density and raw transistor density must scale up in tandem. Some perspective on the magnitude of TSMC's goals include NVIDIA's 80 billion transistor GH100 GPU—among today's largest chips, excluding wafer-scale designs from Cerebras.

Yet TSMC's roadmap calls for more than doubling that, first with over 100 billion transistor monolithic designs, then eventually 200 billion. Of course, yields become more challenging as die sizes grow, which is where advanced packaging of smaller chiplets becomes crucial. Multi-chip module offerings like AMD's MI300X and Intel's Ponte Vecchio already integrate dozens of tiles, with PVC having 47 tiles. TSMC envisions this expansion to chip packages housing more than a trillion transistors via its CoWoS, InFO, 3D stacking, and many other technologies. While the scaling cadence has recently slowed, TSMC remains confident in achieving both packaging and process breakthroughs to meet future density demands. The foundry's continuous investment ensures progress in unlocking next-generation semiconductor capabilities. But physics ultimately dictates timelines, no matter how aggressive the roadmap.

Intel has decided to re-organize its Max series of Data Center GPUs (codenamed Ponte Vecchio), as revealed to Tom's Hardware this week, with a particular model - the Data Center Max GPU 1350 set for removal from the lineup. Industry experts are puzzled by this decision, given that the 1350 has been officially "available" on the market since January 2023, following soon after the announcement of the entire Max range in November 2022. Intel has removed listings and entries for the Data Center GPU Max 1350 from its various web presences.

A (sort of) successor is in the works, Intel has lined up the Data Center Max GPU 1450 for release later in the year. This model will have a trimmed I/O bandwidth - this modification is likely targeting companies in China, where performance standards are capped at a certain level (via U.S. sanctions on GPU exports). An Intel spokesperson provided further details and reasons for rearranging the Max product range: "We launched the Intel Data Center Max GPU 1550 (600 W), which was initially targeted for liquid-cooled solutions only. We have since expanded our support by offering Intel Data Center Max GPU 1550 (600 W) to include air-cooled solutions."

Late on Friday in a newsroom posting by Intel's Interim GM Jeff McVeigh a roadmap uplift was quietly revealed. Rialto Bridge, the process improved version of Ponte Vecchio currently shipping under the Max Series GPU branding, has been pulled from the roadmap in favor of doubling down on the future design code-named Falcon Shores. Rialto Bridge was first announced last May at SC22 as the direct successor to Ponte Vecchio, and was set to begin sampling later this year. In the same post Intel also cancelled Lancaster Sound, their Visual Cloud GPU meant to replace the Arctic Sound Flex series of GPUs based on similar Xe cores to Arc Alchemist. In its stead the follow-up architecture Melville Sound will receive focused development efforts.

Falcon Shores is described as a new foundational chiplet architecture that will integrate more diverse compute tiles, creating what Intel originally dubbed the XPU. This next architectural step would combine what Intel is already doing with products such as Sapphire Rapids and Ponte Vecchio into one CPU+GPU package, and would offer even further flexibility to add other kinds of accelerators. With this roadmap update there is some uncertainty as to whether the XPU designation will make the transition as it is notably absent in the letter. It is clear though that Falcon Shores will directly replace Ponte Vecchio as the next HPC GPU, with or without CPU tiles included.

Supermicro, Inc. (NASDAQ: SMCI), a Total IT Solution Provider for Cloud, AI/ML, Storage, and 5G/Edge, will be showcasing its latest generation of systems that accelerate workloads for the entire Telco industry, specifically at the edge of the network. These systems are part of the newly introduced Supermicro Intel-based product line; the better, faster, and greener systems based on the brand new 4th Gen Intel Xeon Scalable processors (formerly codenamed Sapphire Rapids) that deliver up to 60% better workload-optimized performance. From a performance standpoint these new systems that demonstrate up to 30X faster AI inference speedups on large models for AI and edge workloads with the NVIDIA H100 GPUs. In addition, Supermicro systems support the new Intel Data Center GPU Max Series (formerly codenamed Ponte Vecchio) across a wide range of servers. The Intel Data Center GPU Max Series contains up to 128 Xe-HPC cores and will accelerate a range of AI, HPC, and visualization workloads. Supermicro X13 AI systems will support next-generation built-in accelerators and GPUs up to 700 W from Intel, NVIDIA, and others.

Supermicro's wide range of product families is deployed in a broad range of industries to speed up workloads and allow faster and more accurate decisions. With the addition of purpose-built servers tuned for networking workloads, such as Open RAN deployments and private 5G, the 4th Gen Intel Xeon Scalable processor vRAN Boost technology reduces power consumption while improving performance. Supermicro continues to offer a wide range of environmentally friendly servers for workloads from the edge to the data center.

Intel Corporation today reported fourth-quarter and full-year 2022 financial results. The company also announced that its board of directors has declared a quarterly dividend of $0.365 per share on the company's common stock, which will be payable on March 1, 2023, to shareholders of record as of February 7, 2023.

"Despite the economic and market headwinds, we continued to make good progress on our strategic transformation in Q4, including advancing our product roadmap and improving our operational structure and processes to drive efficiencies while delivering at the low-end of our guided range," said Pat Gelsinger, Intel CEO. "In 2023, we will continue to navigate the short-term challenges while striving to meet our long-term commitments, including delivering leadership products anchored on open and secure platforms, powered by at-scale manufacturing and supercharged by our incredible team."

Intel today marked one of the most important product launches in company history with the unveiling of 4th Gen Intel Xeon Scalable processors (code-named Sapphire Rapids), the Intel Xeon CPU Max Series (code-named Sapphire Rapids HBM) and the Intel Data Center GPU Max Series (code-named Ponte Vecchio), delivering for its customers a leap in data center performance, efficiency, security and new capabilities for AI, the cloud, the network and edge, and the world's most powerful supercomputers.

Working alongside its customers and partners with 4th Gen Xeon, Intel is delivering differentiated solutions and systems at scale to tackle their biggest computing challenges. Intel's unique approach to providing purpose-built, workload-first acceleration and highly optimized software tuned for specific workloads enables the company to deliver the right performance at the right power for optimal overall total cost of ownership. Additionally, as Intel's most sustainable data center processors, 4th Gen Xeon processors deliver customers a range of features for managing power and performance, making the optimal use of CPU resources to help achieve their sustainability goals.

Supermicro, Inc., a Total IT Solution Provider for Cloud, AI/ML, Storage, and 5G/Edge, at the 2022 Super Computing Conference is unveiling the most extensive portfolio of servers and storage systems in the industry based on the upcoming 4th Gen Intel Xeon Scalable processor, formerly codenamed Sapphire Rapids. Supermicro continues to use its Building Block Solutions approach to deliver state-of-the-art and secure systems for the most demanding AI, Cloud, and 5G Edge requirements. The systems support high-performance CPUs and DDR5 memory with up to 2X the performance and capacities up to 512 GB DIMMs and PCIe 5.0, which doubles I/O bandwidth. Intel Xeon CPU Max Series CPUs (formerly codenamed Sapphire Rapids HBM High Bandwidth Memory (HBM)) is also available on a range of Supermicro X13 systems. In addition, support for high ambient temperature environments at up to 40° C (104° F), with servers designed for air and liquid cooling for optimal efficiency, are rack-scale optimized with open industry standard designs and improved security and manageability.

"Supermicro is once again at the forefront of delivering the broadest portfolio of systems based on the latest technology from Intel," stated Charles Liang, president and CEO of Supermicro. "Our Total IT Solutions strategy enables us to deliver a complete solution to our customers, which includes hardware, software, rack-scale testing, and liquid cooling. Our innovative platform design and architecture bring the best from the 4th Gen Intel Xeon Scalable processors, delivering maximum performance, configurability, and power savings to tackle the growing demand for performance and energy efficiency. The systems are rack-scale optimized with Supermicro's significant growth of rack-scale manufacturing of up to 3X rack capacity."

The swanky new Intel Data center Max GPU "Ponte Vecchio" is the company's first product to implement the 12+4 pin ATX 12VHPWR power connector, which the company helped design as part of the ATX 3.0 spec. The PCI-Express add-in card (AIC) form-factor variant of the GPU comes with a single 12VHPWR connector that can deliver up to 600 W of power with 100% excursions within small fractions of time (as prescribed in the ATX 3.0 spec). The card elegantly positions the connector at the tail end of the PCB, where while it might obstruct the air intake slightly, it would still ensure that the connectors aren't bent at odd angles. More importantly, the positioning of the connector ensures a bunch of these cards can be installed in 4U server enclosures (without adding 3.5 cm to the Z-height).

The first GPU maker to implement the 12VHPWR is NVIDIA, with its "Ampere" GeForce RTX 3090 Ti, doubling down on it with the RTX 4090 and soon-to-launch RTX 4080. The connector's implementation heaped bad press over the past few weeks, particularly with the adapter that converts four 8-pin PCIe power connectors to an 12VHPWR; which is allegedly flimsy in the face of aggressive bending for cable-management; with RTX 4090 users on social-media reporting burnt adapters and power connectors on card due to improper mechanical contact from the cable bending/strain. The cable-management standards for servers are different from those of DIY gaming PCs, with many server PSUs still wiring unsleeved "mustard-and-ketchup" cables.

In advance of Supercomputing '22 in Dallas, Intel Corporation has introduced the Intel Max Series product family with two leading-edge products for high performance computing (HPC) and artificial intelligence (AI): Intel Xeon CPU Max Series (code-named Sapphire Rapids HBM) and Intel Data Center GPU Max Series (code-named Ponte Vecchio). The new products will power the upcoming Aurora supercomputer at Argonne National Laboratory, with updates on its deployment shared today.

The Xeon Max CPU is the first and only x86-based processor with high bandwidth memory, accelerating many HPC workloads without the need for code changes. The Max Series GPU is Intel's highest density processor, packing over 100 billion transistors into a 47-tile package with up to 128 gigabytes (GB) of high bandwidth memory. The oneAPI open software ecosystem provides a single programming environment for both new processors. Intel's 2023 oneAPI and AI tools will deliver capabilities to enable the Intel Max Series products' advanced features.

The U.S. Government has imposed restrictions on the export of AI compute GPUs to China and Russia without Government-authorization in the form of a waiver or a license. This impacts sales of products such as the NVIDIA A100, H100; AMD Instinct MI100, MI200; and the upcoming Intel "Ponte Vecchio," among others. The restrictions came to light when NVIDIA on Wednesday disclosed that it has received a Government notification about licensing requirements for export of its AI compute GPUs to Russia and China.

The notification doesn't specify the A100 and H100 by name, but defines AI inference performance thresholds to meet the licensing requirements. The Government wouldn't single out NVIDIA, and so competing products such as the AMD MI200 and the upcoming Intel Xe-HP "Ponte Vecchio" would fall within these restrictions. For NVIDIA, this is impacts $400 million in TAM, unless the Government licenses specific Russian and Chinese customers to purchase these GPUs from NVIDIA. Such trade restrictions usually come with riders to prevent resale or transshipment by companies outside the restricted region (eg: a distributor in a third waived country importing these chips in bulk and reselling them to these countries).

Intel's upcoming Meteor Lake (MTL) processor is set to deliver a wide range of exciting solutions, with the first being the Intel 4 manufacturing node. However, today we have some interesting Linux kernel patches that indicate that Meteor Lake will have a dedicated "Standalone Media" Graphics Technology (GT) block to process video/audio. Moving encoding and decoding off GPU to a dedicated media engine will allow MTL to play back video without the GPU, and the GPU can be used as a parallel processing powerhouse. Features like Intel QuickSync will be built into this unit. What is interesting is that this unit will be made on a separate tile, which will be fused with the rest using tile-based manufacturing found in Ponte Vecchio (which has 47 tiles).

Intel Linux PatchesStarting with [Meteor Lake], media functionality has moved into a new, second GT at the hardware level. This new GT, referred to as "standalone media" in the spec, has its own GuC, power management/forcewake, etc. The general non-engine GT registers for standalone media start at 0x380000, but otherwise use the same MMIO offsets as the primary GT.

Standalone media has a lot of similarity to the remote tiles present on platforms like [Xe HP Software Development Vehicle] and [Ponte Vecchio], and our i915 [kernel graphics driver] implementation can share much of the general "multi GT" infrastructure between the two types of platforms.

With AMD and NVIDIA launching its next-generation HPC compute architectures, "Hopper" and CDNA2, it began seeming like Intel's ambitious "Ponte Vecchio" accelerator based on the Xe-HP architecture, has missed the time-to-market bus. Intel doesn't think so, and in its Hot Chips 34 presentation, disclosed some of the first detailed performance claims that—at least on paper—put the "Hopper" H100 accelerator's published compute performance numbers to shame. We already had some idea of how Ponte Vecchio would perform this spring, at Intel's ISC'22 presentation, but the company hadn't finalized the product's power and thermal characteristics, which are determined by its clock-speed and boosting behavior. Team blue claims to have gotten over the final development hurdles, and is ready with some big numbers.

Intel claims that in classic FP32 (single-precision) and FP64 (double-precision) floating-point tests, its silicon is highly competitive with the H100 "Hopper," with the company claiming 52 TFLOP/s FP32 for the "Ponte Vecchio," compared to 60 TFLOP/s for the H100; and a significantly higher 52 TFLOP/s FP64 for the "Ponte Vecchio," compared to 30 TFLOP/s for the H100. This has to do with the SIMD units of the Xe-HP architecture all being natively capable of double-precision floating-point operations; whereas NVIDIA's architecture typically relies on FP64-specialized streaming multiprocessors.

Hot Chips 34, the upcoming semiconductor conference from Sunday, August 21 to Tuesday, August 23, 2022, will feature many significant contributions from folks like Intel, AMD, Tesla, and NVIDIA. Today, thanks to Intel's registration at the event, we discovered that the company would present its work on Meteor Lake and Arrow Lake processors with the novel Foveros 3D packaging. The all-virtual presentation from Intel will include talks about Ponte Vecchio GPU and its architecture, system, and software; Meteorlake and Arrowlake 3D Client Architecture Platform with Foveros; and some Xeon D and FPGA presentations. You can see the official website here for a complete list of upcoming talks.

As a little reminder, Meteor Lake is supposed to arrive next year, replacing the upcoming Raptor Lake design, and it has already ahs been pictured, which you can see below. The presentation will be recorded and all content posted on Hot Chips's website for non-attendees to catch up on.

Intel has allowed the media to get a closer look at the next generation of silicon that will power millions of systems in years to come during its private Vision event. PC Watch, a Japanese tech media, managed to get some shots of the upcoming Meteor Lake, Sapphire Rapids, and Ponte Vecchio processors. Starting with Meteor Lake, Intel has displayed two packages for this processor family. The first one is the ultra-compact, high-density UP9 package used for highly compact mobile systems, and it is made out of silicon with minimal packaging to save space. The second one is a traditional design with more oversized packaging, designed for typical laptop/notebook configurations.

During the International Solid-State Circuits Conference (ISSCC) 2022, Intel gave us a more significant look at its upcoming Ponte Vecchio HPC accelerator and how it operates. So far, Intel convinced us that the company created Ponte Vecchio out of 47 tiles glued together in one package. However, the ISSCC presentation shows that the accelerator is structured rather interestingly. There are 63 tiles in total, where 16 are reserved for compute, eight are used for RAMBO cache, two are Foveros base tiles, two represent Xe-Link tiles, eight are HBM2E tiles, and EMIB connection takes up 11 tiles. This totals for about 47 tiles. However, an additional 16 thermal tiles used in Ponte Vecchio regulate the massive TDP output of this accelerator.

What is interesting is that Intel gave away details of the RAMBO cache. This novel SRAM technology uses four banks of 3.75 MB groups total of 15 MB per tile. They are connected to the fabric at 1.3 TB/s connection per chip. In contrast, compute tiles are connected at 2.6 TB/s speeds to the chip fabric. With eight RAMBO cache tiles, we get an additional 120 MB SRAM present. The base tile is a 646 mm² die manufactured in Intel 7 semiconductor process and contains 17 layers. It includes a memory controller, the Fully Integrated Voltage Regulators (FIVR), power management, 16-lane PCIe 5.0 connection, and CXL interface. The entire area of Ponte Vecchio is rather impressive, as 47 active tiles take up 2,330 mm², whereas when we include thermal dies, the total area jumps to 3,100 mm². And, of course, the entire package is much larger at 4,844 mm², connected to the system with 4,468 pins.

At Intel's 2022 Investor Meeting, Chief Executive Officer Pat Gelsinger and Intel's business leaders outlined key elements of the company's strategy and path for long-term growth. Intel's long-term plans will capitalize on transformative growth during an era of unprecedented demand for semiconductors. Among the presentations, Intel announced product roadmaps across its major business units and key execution milestones, including: Accelerated Computing Systems and Graphics, Intel Foundry Services, Software and Advanced Technology, Network and Edge, Technology Development, More: For more from Intel's Investor Meeting 2022, including the presentations and news, please visit the Intel Newsroom and Intel.com's Investor Meeting site.

Intel and TSMC are positioning themselves as two competing foundries for a significant period. However, as the difficulties in semiconductor manufacturing rise, the collaboration of the two seems inevitable. Not because Intel is eyeing TSMC's clients, but because of the race to produce the most minor and best possible semiconductor node. We already know that Intel plans to use some of TSMC's nodes for its Ponte Vecchio accelerator that contains 47 tiles. However, we didn't realize just how big the contract between the two companies was. According to the latest report from DigiTimes, Intel is supposed to become one of the top three clients at TSMC.

As the report notes, the collaboration should extend to at least TSMC's 2 nm node, expected in 2025. After that, the state of semiconductors is unknown. Intel has a solid chance to be in the top three customers in 2023 and become one of the primary sources of profit for the Taiwanese giant. We are excited to see how this prediction plays out and hope to hear more from both in the future.

Intel has dropped plans to build Xe-HP server GPUs commercially. This line of products would have powered cloud-based graphics rendering instances, for cloud-gaming or cloud-rendering applications. An announcement to this effect came from Raja Koduri, overseeing the development and monetization of Xe. Koduri stated that Xe-HP based instances were originally set up to power Intel's oneAPI devcloud as a software development vehicle for oneAPI and the upcoming Aurora supercomputer of the Argonne National Laboratory.

The company will now focus on Xe as a compute accelerator in the form of Xe-HPC "Ponte Vecchio," and discrete graphics in the client segment, leveraging the Xe-HPG graphics architecture. The smallest derivatives, the Xe-LP, powers integrated graphics solutions found in the company's Core processors (11th Gen and later). Back in the August 2021 Architecture Day presentation, Intel's technical brief for Xe HPC revealed that the silicon itself features certain on-die hardware relevant to graphics rendering (more here). This would have gone on to power the Xe-HP server GPU solutions.

Intel's Aurora supercomputer is a $500 million contract with the US Department of Energy to deliver an exascale supercomputer for Argonne National Laboratory. The project aims to build a machine capable of cranking over one ExaFLOP of computing at sustained workloads. The supercomputer aims to reach two ExaFLOPs of computing power once the installation system is completed and powered. The contract bound Intel to create accelerators that are powerful enough to achieve this magical number. However, they left Intel with room to do a little bit extra. With Ponte Vecchio GPU behind the project, it seems like the GPU is performing better than expected.

According to Intel's CEO, Pat Gelsinger, the system will reach over 2 ExaFLOPs at peak and a bit below in sustained workloads. As per preliminary calculations done by The Next Platform, the system's estimations point towards 2.43 ExaFLOPs peak and around 1.7 ExaFLOPs in sustained workloads at Double-precision floating-point format math, aka FP64. The system will utilize Intel Xeon Sapphire Rapids processors with HBM memory and the powerful Ponte Vecchio GPU with 47 tiles and over 100 billion transistors.

SiPearl, the designer of the high computing power and low consumption microprocessor that will be the heart of European supercomputers, has entered into a partnership with Intel in order to offer a common offer dedicated to the first exascale supercomputers in Europe. This partnership will offer their European customers the possibility of combining Rhea, the high computing power and low consumption microprocessor developed by SiPearl, with Intel's Ponte Vecchio accelerator, thus creating a high performance computing node that will promote the deployment of the exascale supercomputing in Europe.

To enable this powerful combination, SiPearl plans to use and optimize for its Rhea microprocessor the open and unified programming interface, oneAPI, created by Intel. Using this single solution across the entire heterogeneous compute node, consisting of Rhea and Ponte Vecchio, will increase developer productivity and application performance.

AMD is preparing an update to its compute accelerator lineup with the new MI250X. Based on the CDNA2 architecture, and built on existing 7 nm node, the MI250X will be accompanied by a more affordable variant, the MI250. According to leaks put out by ExecutableFix, the MI250X packs a whopping 110 compute units (7,040 stream processors), running at 1.70 GHz. The package features 128 GB of HBM2E memory, and a package TDP of 500 W. As for speculative performance numbers, it is expected to offer double-precision (FP64) throughput of 47.9 TFLOP/s, ditto full-precision (FP32), and 383 TFLOP/s half-precision (FP16 and BFLOAT16). AMD's MI200 "Aldebaran" family of compute accelerators are expected to square off against Intel's "Ponte Vecchio" Xe-HPC, and NVIDIA Hopper H100 accelerators in 2022.