Intel in its 2021 Architecture Day presentation put out fine technical details of its Xe HPC Ponte Vecchio accelerator, including some [very] preliminary performance claims for its current A0-silicon-based prototype. The prototype operates at 1.37 GHz, but achieves out at least 45 TFLOPs of FP32 throughput. We calculated the clock speed based on simple math. Intel obtained the 45 TFLOPs number on a machine running a single Ponte Vecchio OAM (single MCM with two stacks), and a Xeon "Sapphire Rapids" CPU. 45 TFLOPs sees the processor already beat the advertised 19.5 TFLOPs of the NVIDIA "Ampere" A100 Tensor Core 40 GB processor. AMD isn't faring any better, with its production Instinct MI100 processor only offering 23.1 TFLOPs FP32.

Intel has begun sampling its Xe-HPG (High performance Gaming) products to ecosystem partners, which will allow them to verify performance, power, stability and board characteristics that are necessary variables in product development and launch. The information comes courtesy of Intel, who has updated its graphics product roadmap regarding DG2 sampling and for its Xe-HPC (High Performance Computing) products as well. Xe HPC products (codenamed Ponte Vecchio after a beautiful Florentine bridge) have now achieved power-on capabilities and are undergoing validation before subsequent steps in the hardware development workflow.

At the 2021 International Supercomputing Conference (ISC) Intel is showcasing how the company is extending its lead in high performance computing (HPC) with a range of technology disclosures, partnerships and customer adoptions. Intel processors are the most widely deployed compute architecture in the world's supercomputers, enabling global medical discoveries and scientific breakthroughs. Intel is announcing advances in its Xeon processor for HPC and AI as well as innovations in memory, software, exascale-class storage, and networking technologies for a range of HPC use cases.

"To maximize HPC performance we must leverage all the computer resources and technology advancements available to us," said Trish Damkroger, vice president and general manager of High Performance Computing at Intel. "Intel is the driving force behind the industry's move toward exascale computing, and the advancements we're delivering with our CPUs, XPUs, oneAPI Toolkits, exascale-class DAOS storage, and high-speed networking are pushing us closer toward that realization."

Intel's upcoming Ponte Vecchio graphics card is set to be the company's most powerful processor ever designed, and the chip is indeed looking like an engineering marvel. From Intel's previous teasers, we have learned that Ponte Vecchio is built using 47 "magical tiles" or 47 dies which are responsible either for computing elements, Rambo Cache, Xe links, or something else. Today, we are getting a new piece of information coming from Igor's LAB, regarding the Ponte Vecchio and some of its design choices. For starters, the GPU will be a heterogeneous design that consists out of many different nodes. Some parts of the GPU will be manufactured on Intel's 10 nm SuperFin and 7 nm technologies, while others will use TSMC's 7 nm and 5 nm nodes. The smaller and more efficient nodes will probably be used for computing elements. Everything will be held together by Intel's EMIB and Foveros 3D packaging.

Next up, we have information that this massive Intel processor will be accountable for around 600 Watts of heat output, which is a lot to cool. That is why in the leaked renders, we see that Intel envisioned these processors to be liquid-cooled, which would make the cooling much easier and much more efficient compared to air cooling of such a high heat output. Another interesting thing is that the Ponte Vecchio is designed to fit inside OAM (OCP Accelerator Module) form factor, an alternative to the regular PCIe-based accelerators in data centers. OAM is used primarily by hyper scalers like Facebook, Amazon, Google, etc., so we imagine that Intel already knows its customers before the product even hits the market.

Today, Lenovo in partnership with Intel has announced that Leibniz Supercomputing Centre (LRZ) is building a supercomputer powered by Intel's next-generation technologies. Specifically, the supercomputer will use Intel's Sapphire Rapids CPUs in combination with the highly-teased Ponte Vecchio GPUs to power the applications running at Leibniz Supercomputing Centre. Along with the various processors, the LRZ will also deploy Intel Optane persistent memory to process the huge amount of data the LRZ has and is producing. The integration of HPC and AI processing will be enabled by the expansion of LRZ's current supercomputer called SuperMUG-NG, which will receive an upgrade in 2022, which will feature both Sapphire Rapids and Ponte Vecchio.

Mr. Raja Koduri, Intel graphics guru, has on Twitter teased that this supercomputer installment will represent a combination of Sapphire Rapids, Ponte Vecchio, Optane, and One API all in one machine. The system will use over one petabyte of Distributed Asynchronous Object Storage (DAOS) based on the Optane technologies. Then, Mr. Koduri has teased some Ponte Vecchio eye candy, which is a GIF of tiles combining to form a GPU, which you can check out here. You can also see some pictures of Ponte Vecchio below.

Raja Koduri of Intel has today posted an interesting video on his Twitter account. Showing one of the greatest engineering marvels Intel has ever created, Mr. Koduri has teased what is to come when the company launches the Xe-HPC Ponte Vecchio graphics card designed for high-performance computing workloads. Showcased today was the "petaflops in your palm" chip, designed to run AI workloads with a petaflop of computing power. Having over 100 billion transistors, the chip uses as much as 47 tiles combined in the most advanced packaging technology ever created by Intel. They call them "magical tiles", and they bring logic, memory, and I/O controllers, all built using different semiconductor nodes.

Mr. Koduri also pointed out that the chip was born after only two years after the concept, which is an awesome achievement, given that the research of the new silicon takes years. The chip will be the heart of many systems that require massive computational power, especially the ones like AI. Claiming to have the capability to perform quadrillion floating-point operations per second (one petaflop), the chip will be a true monster. So far we don't know other details like the floating-point precision it runs at with one petaflop or the total power consumption of those 47 tiles, so we have to wait for more details.More pictures follow.

Intel and Argonne National Laboratory are collaborating on the co-design and validation of exascale-class applications using graphics processing units (GPUs) based on Intel Xe-HP microarchitecture and Intel oneAPI toolkits. Developers at Argonne are tapping into Intel's latest programming environments for heterogeneous computing to ensure scientific applications are ready for the scale and architecture of the Aurora supercomputer at deployment.

"Our close collaboration with Argonne is enabling us to make tremendous progress on Aurora, as we seek to bring exascale leadership to the United States. Providing developers early access to hardware and software environments will help us jumpstart the path toward exascale so that researchers can quickly start taking advantage of the system's massive computational resources." -Trish Damkroger, Intel vice president and general manager of High Performance Computing.

TSMC has been the backbone of silicon designers for a long time. Whenever you question where you can use the latest technology and get some good supply capacity, TSMC got everyone covered. That case seems to be similar to Intel and its struggles. When Intel announced that its 7 nm semiconductor node is going to be delayed a full year, the company's customers and contractors surely became worried about the future releases of products and their delivery, like the case is with Aurora exascale supercomputer made for Argonne National Laboratory, which relies on Intel's 7 nm Ponte Vecchio graphics cards for most of the computation power.

To manage to deliver this, Intel is reportedly in talks with TSMC to prepare capacity for the GPUs and deliver them on time. However, according to industry sources of DigiTimes, TSMC is unlikely to build additional capacity for Intel, besides what it can deliver now. According to those sources, TSMC does not see Intel as a long-term customer and it is unknown what treatment will Intel get from TSMC. Surely, Intel will be able to make a deal with TSMC and secure enough of the present capacity for delivering next-generation processors.

To support its efforts to build a competitive consumer GPU lineup under the Xe brand, which Intel likes to call its "Odyssey," the company scored another higher-up from AMD, this time Ali Ibrahim. He joined Intel this month as a vice-president within the Architecture, Graphics and Software group, although the company didn't specify his responsibilities. "We are thrilled that Ali has joined Intel as Vice President, Platform Architecture and Engineering - dGPUs to be part of the exciting Intel Xe graphics journey," said an Intel spokesperson in a comment to CRN.

During his 13-year tenure at AMD, Ali Ibrahim was the chief-architect of the company's cloud gaming and console SoC businesses, which provides valuable insight into Intel's breakneck efforts to build high-end discrete GPUs (something it lacked for the past two decades). Intel is the only other company that is capable of building semi-custom chips for someone like Microsoft or Sony as the inventor of x86, provided it has a GPU that can match AMD's in the console space. Likewise, with gaming taking baby steps to the cloud as big players such as Google betting on it, Intel sees an opportunity for cloud gaming GPUs that aren't too different from its "Ponte Vecchio" scalar processors. The transfer of talent isn't one-way, as AMD recently bagged Intel's server processor lead Dan McNamara to head the EPYC brand.

Will Intel even make client-segment gaming discrete GPUs now? Because the GPU marketing gurus Intel snatched from AMD to sell them, Chris Hook and Heather Lennon, are reportedly no longer with the company. The two are on their way to an unnamed startup. This, according to a sensational Charlie Demerjian report citing company sources. These exits closely follow that of another valuable chip marketing honcho, John Carvill, who joined Austin-based startup Nuvia, which is designing ASICs and SoCs for the data-center of the future.

Hook and Lennon were responsible for the PR dexterity AMD RTG enjoyed through its ups and downs this decade. With RTG head Raja Koduri leaving for Intel to head its GPU development project, his former comrades at RTG soon followed. The flight of GPU marketing talent out of Intel at this stage could be the first of many hints that Intel has made a big decision with regards to how it plans to monetize Raja's work. "Ponte Vecchio" is Intel's ambitious GPU compute processor designed primarily for HPC and AI workloads. There's tumbleweed coming out of Intel on "Arctic Sound" since Q2-2019, a contraption that more closely resembles graphics cards as you know it.

At Supercomputing 2019, Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with new additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from today's single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from today's limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

Intel's first Xe GPU built on the company's 7 nm silicon fabrication process will be codenamed "Ponte Vecchio," according to a VideoCardz report. These are not gaming GPUs, but rather compute accelerators designed for exascale computing, which leverage the company's CXL (Compute Express Link) interconnect that has bandwidth comparable to PCIe gen 4.0, but with scalability features slated to come out with future generations of PCIe. Intel is preparing its first enterprise compute platform featuring these accelerators codenamed "Project Aurora," in which the company will exert end-to-end control over not just the hardware stack, but also the software.

"Project Aurora" combines up to six "Ponte Vecchio" Xe accelerators with up to two Xeon multi-core processors based on the 7 nm "Sapphire Rapids" microarchitecture, and OneAPI, a unifying API that lets a single kind of machine code address both the CPU and GPU. With Intel owning the x86 machine architecture, it's likely that Xe GPUs will feature, among other things, the ability to process x86 instructions. The API will be able to push scalar workloads to the CPU, and and the GPU's scalar units, and vector workloads to the GPU's vector-optimized SIMD units. Intel's main pitch to the compute market could be significantly lowered software costs from API and machine-code unification between the CPU and GPU.Image Courtesy: Jan Drewes