Memory and Platform I/O

As a multi-chip module of four dies with a 128-bit wide (dual-channel) DDR4 memory bus, each, EPYC has each of the four dies wired out to the socket. The processor hence features a vast eight-channel (512-bit wide) DDR4 memory interface. Unlike on Intel platforms where you can add up to 3 DIMMs per channel, AMD is restricting you to 2 DIMMs per channel, probably keeping in mind limited board footprint. That's still up to 16 DIMMs per socket, with an upper limit of 2 TB.


A wide range of DIMMs are supported, including RDIMM, LRDIMM, NVDIMM-N, and 3DS-DIMM. The standard frequency is DDR4-2666, which works out to a GPU-rivaling 171 GB/s of memory bandwidth per socket. While L2 caches are exclusive to the core and L3 are exclusive to the CCX, memory access is shared across the socket, and among sockets, over AMD's bi-directional InfinityFabric interconnect (more on this later).



Much to AMD's advantage, each of the four dies on the EPYC MCM has an integrated core logic. This means the PCI-Express lane budget of each die is linearly scaled to give you a class-leading 128 PCIe gen 3.0 lanes. The applications of these PCIe lanes is endless. A vast number of high-bandwidth devices, such as professional graphics cards, HPC compute accelerators, machine-learning accelerators, NVMe SSDs, 100 Gbps fiber NICs, and more, can be deployed. Each chip further has a small integrated southbridge with two SATA 6 Gbps ports and six USB 3.0 ports; some of these are wired out.