Tuesday, December 22nd 2015
Samsung to Fab AMD "Zen" and "Arctic Islands" on its 14 nm FinFET Node
It has been confirmed that Samsung will be AMD's foundry partner for its next generation GPUs. It has been reported that AMD's upcoming "Arctic Islands" family of GPUs could be built on the 14 nanometer FinFET LPP (low-power Plus) process. AMD's rival NVIDIA, meanwhile, is building its next-gen "Pascal" GPU family on 16 nanometer FinFET node, likely at its traditional foundry partner TSMC.
It gets better - not only will Samsung manufacture AMD's next-gen GPUs, but also its upcoming "Zen" family of CPUs, at least a portion of it. AMD is looking to distribute manufacturing loads between two foundries, Samsung and GlobalFoundries, perhaps to ensure that foundry-level teething trouble doesn't throw its product launch cycle off the rails. One of the most talked about "Arctic Islands" GPUs is codenamed "Greenland," likely a successor to "Fiji." Sales of some of the first chips - GPUs or CPUs - made at Samsung, will begin some time in Q3 2016. Some of the other clients for Samsung's 14 nm FinFET node are Apple and Qualcomm. The company plans to speed up development of its more advanced 10 nm node to some time in 2017.
Source:
ETNews
It gets better - not only will Samsung manufacture AMD's next-gen GPUs, but also its upcoming "Zen" family of CPUs, at least a portion of it. AMD is looking to distribute manufacturing loads between two foundries, Samsung and GlobalFoundries, perhaps to ensure that foundry-level teething trouble doesn't throw its product launch cycle off the rails. One of the most talked about "Arctic Islands" GPUs is codenamed "Greenland," likely a successor to "Fiji." Sales of some of the first chips - GPUs or CPUs - made at Samsung, will begin some time in Q3 2016. Some of the other clients for Samsung's 14 nm FinFET node are Apple and Qualcomm. The company plans to speed up development of its more advanced 10 nm node to some time in 2017.
53 Comments on Samsung to Fab AMD "Zen" and "Arctic Islands" on its 14 nm FinFET Node
Previous poster was also wrong. IBM and GF licensed Samsung 14nm FF ... but IBM never implemented it, and GF now own the IBM foundry business anyway. Also, GF 14nm FF LPP isn't copy exact .. it was originally supposed to be but they used different tools to save money ... hence delays and probably yield / volume / cost issues which got AMD to finally make the leap. Furthermore TSMC has absolutely nothing to do with it. They plow their own (lone) furrow.
TSMC 16nm FF+ and Samsung / GF 14nm FF LPP are completely different. FF+ is a high power process. LPP is a low power (but not SLP) process. So AMD / NVIDIA can't swap around without huge cost, redesigns and headaches ... also this predicates a situation where there is finally a major difference in lithography between AMD and NVIDIA - low power process vs high power process; former is likely to have way higher yields and lower costs .. latter will probably clock higher but suffer badly in cost and yields ... and TSMC's FF+ process will have very, very limited / contested capacity at first, unlike Samsung LPP. Samsung's high power (and refined versions of LPE / LPP) come at the very end of '16, though I'd guess the LPE / LPP revisions will take priority over the HP version as AMD have gone with LP designs. Carrizo desktop and AM4 will probably be launched and available in April or May. Zen likely launches at Computex with availability as soon as they can get it afterwards - some time in Q3. Arctic Islands at E3 with ~immediate availability.
I think the original plan was for Zen desktop (non-APU) to launch with AM4, before AI, so that people could build a new system before the new graphics cards. It'll be the other way around now.
Either way, that isn't long. Especially when neither NVIDIA nor Intel have anything coming up in the mean time.
Also, the news is interesting and should have good effects on the performance/watt metric.
Still, if AMD pull a blinder and both are superb products, then they can of course turn things around.
There were 4 major partners, and a host of minor parties. IBM, GF, Samsung, ST-M. IBM are out of the business and their foundry (mainly serving custom / semi-custom workstation chips) is owned by GF these days. ST are out entirely (though they continue to develop FD-SOI and license it to others).
Samsung and GF remain.
Dirk decided that AMD wouldn't develop a strategy for the handheld GPU ( smartphones mainly) because he was pursuing high margin areas - basically servers (which is where his expertise lie). Dirk and the board gambled on Bulldozer hitting its targets to save the company rather than invest in low margin GPU IP for phones and other peripheral business (as Dirk saw it). Not necessarily. The cross-license agreement has a year grace period built in to allow a new owner to renegotiate. Not that it matters. Samsung is fully invested in ARM and I would doubt it has any use for x86 in its current strategy.
This is the article I wrote about it in 2010 semiaccurate.com/2010/10/14/common-platform-alliance-key-foundry-success/
So Intel and TSMC might not have been part of the Common Platform Alliance, but they did work with GloFo, Samsung and IBM to work towards more common platforms hothardware.com/news/global-alliance-intel-ibm-globalfoundries-tsmc-and-samsung-announce-new-partnership
As for Samsung 14nm vs TSMC 16nm... a ~3.3 billion transistor A9 is a far cry from a ~17 billion transistor Pascal (+ HBM). I'm sure Zen and Arctic Islands will be decent, but unless TSMC has really slipped up, Pascal will be better than decent - and AMD needs the latter, not the former, if its CPU business is to survive.
The scaling ability of newer low nm processes have been as limited by the memory interface as anything else, thus driving the need for lower voltage memory at the same and or higher performance levels...... why you ask? ODT On Die Termination, when the memory controller moved onto the silicon itself, the memory voltage has to be dealt with and stepped down to core voltage, and that is the job of resistors built into the die, and the larger amount of memory the more currant flow to maintain signal integrity, the more currant to terminate to prevent capacitive induction, the more heat....
Same goes for the number PCIe interface lanes built into the GPU core, so the ability to have a smaller node counts as much for the actual transistors doing computation as it does for the interfaces and power consumption for them.
I do imagine that AMD has a series of cards built on the LPP method that is pushing its limits, and possibly even why the release date is later on them, to work on power inside the core, as it's limited by the architecture as much as the process.