Friday, March 17th 2017
AMD Ryzen Infinity Fabric Ticks at Memory Speed
Memory clock speeds will go a long way in improving the performance of an AMD Ryzen processor, according to new information by the company, which reveals that Infinity Fabric, the high-bandwidth interconnect used to connect the two quad-core complexes (CCXs) on 6-core and 8-core Ryzen processors with other uncore components, such as the PCIe root-complex, and the integrated southbridge; is synced with the memory clock. AMD made this revelation in a response to a question posed by Reddit user CataclysmZA.
Infinity Fabric, a successor to HyperTransport, is AMD's latest interconnect technology that connects the various components on the Ryzen "Summit Ridge" processor, and on the upcoming "Vega" GPU family. According to AMD, it is a 256-bit wide bi-directional crossbar. Think of it as town-square for the chip, where tagged data and instructions change hands between the various components. Within the CCX, the L3 cache performs some inter-core connectivity. The speed of the Infinity Fabric crossbar on a "Summit Ridge" Ryzen processor is determined by the memory clock. When paired with DDR4-2133 memory, for example, the crossbar ticks at 1066 MHz (SDR, actual clock). Using faster memory, according to AMD, hence has a direct impact on the bandwidth of this interconnect.
Source:
CataclysmZA on Reddit
Infinity Fabric, a successor to HyperTransport, is AMD's latest interconnect technology that connects the various components on the Ryzen "Summit Ridge" processor, and on the upcoming "Vega" GPU family. According to AMD, it is a 256-bit wide bi-directional crossbar. Think of it as town-square for the chip, where tagged data and instructions change hands between the various components. Within the CCX, the L3 cache performs some inter-core connectivity. The speed of the Infinity Fabric crossbar on a "Summit Ridge" Ryzen processor is determined by the memory clock. When paired with DDR4-2133 memory, for example, the crossbar ticks at 1066 MHz (SDR, actual clock). Using faster memory, according to AMD, hence has a direct impact on the bandwidth of this interconnect.
95 Comments on AMD Ryzen Infinity Fabric Ticks at Memory Speed
less is more
better to use like 8 GB of expensive super fast memory to get more performance then.
What AMD should do is to revive their Radeon memory brand and sell super fast DDR4 memory with only Ryzen profiles at very low cost to push their Ryzen cpu business.
This way gamers are more inclined to upgrade to Ryzen if the can get maximum performance at a reasonable price. What they don't make in the memory business they will gain 10 fold in the cpu business.
Not a big issue per se, but it depends whether memory speeds can be fixed with a simple BIOS update or they require hardware changes.
Programmers must know about cache mechanisms. They can calculate concurrently but must update in one thread. If data are shared by many cores and they update it, there will be total mess, especially in Ryzen.
Optimizing data chunks wrt cache size is required in some instances, but knowing the intricacies of cache's implementation is certainly not a requirement for a programmer.
So if the Windows scheduler handles the threads and L3 cache properly, not moving threads between the two CCX this Infinity Fabric should not be an issue, and AMD said that Windows Scheduler is aware of the Ryzen Architecture.
I'm confused.
And wishful thinking but maybe in the next BIOS updates we could unlink the bus from the memory and overclock it.
If you are not skilled programmer and don't know much about parallel programming, you should write single-threaded programs. Caches always helps you in there.
And you should know the details of hardware if you write performance-critical software, like a game.
Caching has nothing to do with multi-threading. Caching is there to avoid memory read/writes, it doesn't actually care whether the CPU is running 1 or 1,000 threads.
L1 and L2 caches are always split and I know of no one trying to write multithreaded code in order not to upset L1 and L2 caches. If anything, that's a compiler's or a scheduler's job. I don't see why things would be any different when we're talking about L3 cache.
That's where the Infinity Fabric bottleneck takes place and heavily affects performance.
And even so, thread core affinity is typically the responsibility of the OS.
Something is not adding up here. From the information that was floating around it sounded like the Infinite Fabric is the bottleneck due to threads moving between CCX.
But with AMD releasing that statement that nothing wrong with the Windows scheduler it looks like that bus is the bottleneck in all scenarios.
And its sounds like all the memory issues are related to the bus being in sync with the memory.
Looks like a huge overlook on AMD side.
But I'm willing to bet they will offer significant IPC improvement on Zen 2.0 and it will be largely due to addressing the bus speed.
You can thank this new Tech for Ryzen's low cost and massive 32-core brethren. In fact I hope (And expect) AMD to apply this to their GPU archs within a year. Imagine a 1200mm^2 10,000-SP monster gaming card.
It is possible to play the caches like a fiddle (Memtest86+ doesn't disable them), but it's quite difficult and not something that can be done under an OS.
BTW hasn't AMD done something like this before? I think they once had a FSB that was synced with main memory, or had to be for good performance.
But this compromise is just like when we "compromise" and buy whatever CPU we can, even if we know a better one is just around the corner. If we'd wait for the perfect CPU, we'd never buy anything. The same as AMD, if they wanted to fix everything, they'd never release. Because once fixed, the bottleneck would simply move somewhere else, and once that was fixed the bottleneck would move again and so on.