Friday, March 17th 2017
AMD Ryzen Infinity Fabric Ticks at Memory Speed
Memory clock speeds will go a long way in improving the performance of an AMD Ryzen processor, according to new information by the company, which reveals that Infinity Fabric, the high-bandwidth interconnect used to connect the two quad-core complexes (CCXs) on 6-core and 8-core Ryzen processors with other uncore components, such as the PCIe root-complex, and the integrated southbridge; is synced with the memory clock. AMD made this revelation in a response to a question posed by Reddit user CataclysmZA.
Infinity Fabric, a successor to HyperTransport, is AMD's latest interconnect technology that connects the various components on the Ryzen "Summit Ridge" processor, and on the upcoming "Vega" GPU family. According to AMD, it is a 256-bit wide bi-directional crossbar. Think of it as town-square for the chip, where tagged data and instructions change hands between the various components. Within the CCX, the L3 cache performs some inter-core connectivity. The speed of the Infinity Fabric crossbar on a "Summit Ridge" Ryzen processor is determined by the memory clock. When paired with DDR4-2133 memory, for example, the crossbar ticks at 1066 MHz (SDR, actual clock). Using faster memory, according to AMD, hence has a direct impact on the bandwidth of this interconnect.
Source:
CataclysmZA on Reddit
Infinity Fabric, a successor to HyperTransport, is AMD's latest interconnect technology that connects the various components on the Ryzen "Summit Ridge" processor, and on the upcoming "Vega" GPU family. According to AMD, it is a 256-bit wide bi-directional crossbar. Think of it as town-square for the chip, where tagged data and instructions change hands between the various components. Within the CCX, the L3 cache performs some inter-core connectivity. The speed of the Infinity Fabric crossbar on a "Summit Ridge" Ryzen processor is determined by the memory clock. When paired with DDR4-2133 memory, for example, the crossbar ticks at 1066 MHz (SDR, actual clock). Using faster memory, according to AMD, hence has a direct impact on the bandwidth of this interconnect.
95 Comments on AMD Ryzen Infinity Fabric Ticks at Memory Speed
The memory ICs on the DIMM itself run at an even lower clock speed. In this example, is it 300 MHz. DDR4 links at 4x the IC clock. DDR3 also links at 4x the IC clock. DDR2 links at 2x the IC clock. DDR links at 1x the IC clock. The underlying memory chips don't get much faster over time. Mostly they just get more dense.
When data are shared by multiple CCX, the cost is very high. When data are shared by the cores on one CCX, or on a Intel processor, the cost is much lower, but it's still costly. So you shouldn't update shared data carelessly. You should create an update thread and put tasks on it. This can't be done by any scheduler or compiler.
It touches on how developers feel about optimizing for each and every CPU, but there's more interesting stuff in there.
Yes, I realize memory speeds that high are not supported, and AFAIK you can't actually even select memory speeds that high yet. But I'm thinking of the future. Is this interconnect going to become a limitation to memory speed down the road. If they have problems getting the interconnect stable at higher speeds, we might be limited to 3500MT/s memory in the future, which would suck.
I don't see why Infinity Fabric Would become unstable at faster speeds.
Infinity Fabric Has a 256-Bit Quad Channel interface. Or a Bi directional channel. Something like that lok
Increasing clock speed on something always runs at the risk of it becoming unstable.
But I guarantee we will see a 4-core that is just a single CCX. The CCX has no affect on memory channels, the memory controller is not part of the CCX.
I read somewhere that AMD is going to release an update to enable a higher DDR4 multiplier to increase the RAM speed, hence increasing the Infinity Fabric.
Eventually they will release the single CCX 4 cores, probably with a model number bump to something like R3 1250X or something instead of the 1200X.