AssimilatorYou're going to have to substantiate your claim that the Skylake uarch, and its derivatives, have ingrained scalability and security issues. Sunny Cove is a derivative of Skylake, which is a derivative of Sandy Bridge, and the IPC increase from the original SNB parts to those of today are massive. Not to mention that SKL => SNC is supposedly an 18% IPC improvement again... a uarch that can be competitive for nearly a decade sounds pretty scalable to me.

Scalability comes down the to the monolithic die design - To achieve scalability for servers and higher core counts, Intel switched to a completely different ring bus for cores for the first half of last decade, and then upgraded to a more scalable mesh network when that run out of steam. The desktop parts saw almost none of that and they're still essentially the quad-core design of Sandy bridge scaled up to near breaking point at 8 and 10-core SKUs.

As for security, you only have to go back and look at the 'Watergate' moment for Intel - Spectre and Meltdown. Meltdown targeted intel's complete lack of privilege checking for data in the pipeline, so Intel's performance for out-of-order pipeline execution was good, simply because they weren't doing half of the security and data isolation that a responsible design should be doing. AMD and Arm designs are immune to this because AFAIK they have proper privilege checking on any data in cache or other stores in the pipeline for SMT/Hyperthreading.

Spec-ex attacks, of which Spectre was the first and most painful for Intel also don't affect AMD or Arm as badly. They do target a specific architecture, so that regard Intel is a victim of its own popularity, but at the same time the mitigations AMD put out for the first two variants (back when x/y benchmarking was being tested on the mitigation performance impacts) had almost no performance loss on AMD (1-2%) Whilst Intel was seeing double-digit losses from some applications. Without more experience and understanding of exactly how the patches work, I can only guess that Intel had more holes to patch than AMD, which is why they only bothered with some of the exploits (leaving Microsoft to fill in the gaps) and even then the firmware patches they did write offended the Linux crowd - which mattered a lot because a lot of the datacenters hit worst by Spectre were running linux servers on Intel.

yeeeemanNow, moving to architecture, current, as far as I know Intel has the best IPC core with Ice Lake, it is 5-10% better than Zen 2, so get your facts straight.

Do you have an apples-to-apples article I can read for that? I'm not doubting you've read that somewhere but right now there's no direct comparison because Intel haven't managed to get Ice Lake onto desktop. Renoir would be the closest match to Ice Lake as a monolithic die using Zen2 but a big part of Ice Lake was larger caches and Renoir is specifically a cut-down version of Zen2 with smaller caches to keep production costs relevant to the target market. Renoir has a quarter the cache of Mattise, so it's far more reliant on RAM speeds yet is normally paired with DDR4-3200 instead of the LPDDR4X that usually goes with the i7-1065G7. Additionally, I've not seen any fixed-clock tests of Ice Lake as they are all mostly mainstream laptop parts with notoriously useless OEM BIOSes when it comes to benchmarking and tweaking.

If you have a valid link please share, I want to see (real world) how Sunny Cove is doing but there's simply no straight-up comparison I've found that can be extrapolated to how well it would fare on a desktop or server-scale part.

Chrispy_Scalability comes down the to the monolithic die design - To achieve scalability for servers and higher core counts, Intel switched to a completely different ring bus for cores for the first half of last decade, and then upgraded to a more scalable mesh network when that run out of steam. The desktop parts saw almost none of that and they're still essentially the quad-core design of Sandy bridge scaled up to near breaking point at 8 and 10-core SKUs.

I don't see any indication that core interconnect is a limiting factor.

Chrispy_As for security, you only have to go back and look at the 'Watergate' moment for Intel - Spectre and Meltdown. Meltdown targeted intel's complete lack of privilege checking for data in the pipeline, so Intel's performance for out-of-order pipeline execution was good, simply because they weren't doing half of the security and data isolation that a responsible design should be doing. AMD and Arm designs are immune to this because AFAIK they have proper privilege checking on any data in cache or other stores in the pipeline for SMT/Hyperthreading.

Spec-ex attacks, of which Spectre was the first and most painful for Intel also don't affect AMD or Arm as badly. They do target a specific architecture, so that regard Intel is a victim of its own popularity, but at the same time the mitigations AMD put out for the first two variants (back when x/y benchmarking was being tested on the mitigation performance impacts) had almost no performance loss on AMD (1-2%) Whilst Intel was seeing double-digit losses from some applications. Without more experience and understanding of exactly how the patches work, I can only guess that Intel had more holes to patch than AMD, which is why they only bothered with some of the exploits (leaving Microsoft to fill in the gaps) and even then the firmware patches they did write offended the Linux crowd - which mattered a lot because a lot of the datacenters hit worst by Spectre were running linux servers on Intel.

I would imagine by now that all the Spectre and Meltdown mitigations have been implemented in the latest hardware, i.e. ICL, so there really isn't much point in talking about them anymore.

Chrispy_Scalability comes down the to the monolithic die design - To achieve scalability for servers and higher core counts, Intel switched to a completely different ring bus for cores for the first half of last decade, and then upgraded to a more scalable mesh network when that run out of steam. The desktop parts saw almost none of that and they're still essentially the quad-core design of Sandy bridge scaled up to near breaking point at 8 and 10-core SKUs.

Monolithic vs chiplet is entirely different argument for scalability, at least from architecture side of things. Chiplet brings better possible yields and more possible cores at the cost of having to integrate the parts over interconnect that goes in and out of die. Ringbus so far seems better suited for desktop and especially gaming purposes compared to mesh.

Chrispy_As for security, you only have to go back and look at the 'Watergate' moment for Intel - Spectre and Meltdown. Meltdown targeted intel's complete lack of privilege checking for data in the pipeline, so Intel's performance for out-of-order pipeline execution was good, simply because they weren't doing half of the security and data isolation that a responsible design should be doing. AMD and Arm designs are immune to this because AFAIK they have proper privilege checking on any data in cache or other stores in the pipeline for SMT/Hyperthreading.

While Meltdown is a bug, it is not a complete lack of privilege checking. The attack vector for the entire Spectre family is more complex than that. Also, certain ARM designs are vulnerable to Meltdown.
The performance vs security is an interesting argument but I cannot see this being the case, architecturally speaking. And CPUs with Meltdown fix in hardware have not been tested to be slower so that does not seem to be the case in reality either.

AssimilatorI would imagine by now that all the Spectre and Meltdown mitigations have been implemented in the latest hardware, i.e. ICL, so there really isn't much point in talking about them anymore.

They're mostly fixed in hardware for ICL but not completely still.

Also, it's important to remember that the hardware fix means that you're no longer vulnerable even with unpatched firmware/OS but the performance penalties will still be there until Intel actually redesigns the branch prediction from the ground up for Spec-ex attacks.

Their existing architecture has been cracked and these workarounds (be it hardware or software) are basically just to turn off the bits of the architecture that have found to be exploitable. The peformance benefit of those disabled things is not recuperated, it is lost forever to Intel until they create a whole new architecture from the ground up - buying them a few years of safety until the exploiters get experience reverse-engineering and poking it. This is probably one of the reasons Ryzen patches have less of an impact, because it's a much newer design and there's less known about potential attack vectors against it still. I'm sure 1st Gen Ryzen will be less secure in 2025 than it is today, but AMD will not still be recycling 1st Gen Ryzen architecture in 2025 either, unlike Intel with their "Core" microarchitecture which although improved over the last decade, is something that the hackers have been poking at for almost a decade.

Anyway, in looking for a more concrete answer to you, I've discovered (to my dismay) that Sunny Cove isn't much of a brand new architecture redesign. It's still something like 85% Skylake and very much just a rebalancing of the ratios of various Skylake-era subcomponents. It's certainly not the Phenon > Bulldozer > Zen change over the last decade that effectively keeps the hackers at bay (and one reason AMD is on it's third architecture this decade is because the first one was already a decade old in 2010 and the second one was too terrible to carry on with!)

ddarkoIt's interesting that as Apple leaves Intel to go with big.LITTLE with its Apple Silicon chips, Intel is shifting to big.LITTLE as well. People seem pretty intrigued by the possibilities of Apple Silicon, or at least no one seems to be writing it off as a lost cause already just because it's going to be big.LITTLE. Obviously Apple's execution has been a lot better than Intel's in the last few years so it's fair Apple gets the benefit of the doubt while Intel very much needs to prove it can pull another rabbit out of its hat like Core. I guess we will see if Intel can execute.

No one!, I have for years , things are going south IMHO.
Apple wrote themselves off many times in my eyes.

And this could write Intel chips off for me.

ratirtI don't think they can run simultaneously. The main idea with the small cores is, when full blown cores are not needed for light tasks the small cores take over to save power.

It seems like a missed opportunity if that is the case. Keeping the low powered cores running for background processes that don't need tomhe big cores and then firing up the big cores for processes that need the power would be great on a desktop where power budgets are significantly higher would theoretically offer significantly better performance. On a laptop, sure, I can see the benefit, but on the desktop I'd rather have something that can ramp up the frequency of the cores and run them all simultaneously.

Why would they not run simultaneously? Pretty sure they can, in actual usage power management configuration is probably what will throttle some cores down to conserve power. This is what happens to Lakefield cores - they are running simultaneously but at a (very) low frequency which is a power management thing.

yeeeemanIn regards to small cores, what is exactly your point? Tremont has Ivy bridge level of IPC. Zen 1 has Ivy bridge - haswell level of IPC.
If Tremont has IPC comparable to Ivy, this doesn't mean the core is as phat as Skylake...
You can search for die shots, but 4 tremont cores are just a bit more than 1 sunny cove core in die size, so I would estimate 1 tremont core to be 1 third of a skylake core. Given it has ivy bridge level of IPC, that is very impressive.

From what i remember intel Silvermount and AMD Jaguar were both in Conroe IPC territory that was good enough to me.
Conroe to Ivy Bridge is a big jump, do you have any analysis to show me about that? I'm genuinely curious.