Friday, October 16th 2020
AMD Ryzen 5000 Series Features Three Synchronized Memory Clock Domains
A leaked presentation slide by AMD for its Ryzen 5000 series "Zen 3" processors reveals details of the processor's memory interface. Much like the Ryzen 3000 series "Matisse," the Ryzen 5000 series "Vermeer" is a multi-chip module of up to 16 CPU cores spread across two 8-core CPU dies, and a unified I/O die that handles the processor's memory-, PCIe, and SoC interfaces. There are three configurable clock domains that ensure the CPU cores are fed with data at the right speed, and to ensure that the MCM design doesn't pose bottlenecks to the memory performance.
The first domain is fclk or Infinity Fabric clock. Each of the two CCDs (8-core CPU dies) has just one CCX (CPU core complex) with 8 cores, and hence the CCD's internal Infinity Fabric cedes relevance to the IFOP (Infinity Fabric over Package) interconnect that binds the two CCDs and the cIOD (client I/O controller die) together. The next frequency is uclk, or the internal frequency of the dual-channel DDR4 memory controller contained in the cIOD. And lastly, the mclk, or memory clock is the industry-standard DRAM frequency.
The three clock domains, according to AMD, are in a 1:1:1 synchrony, i.e. DRAM SDR clock is the same as uclk and fclk (for example, DDR4-3600 would see the memory real clock, uclk, and fclk run at 1800 MHz. AMD also appears to have increased the fclk limit to 2000 MHz with "Zen 3," so you can run memory clock at up to DDR4-4000 without having to engage the mclk:fclk 1:2 divider, which means DDR4-4000 on "Vermeer" will fetch as much of a real-world performance dividend as DDR4-3800 did for "Matisse." With AMD Ryzen, memory overclocking has been an effective way to improve overall system performance, due to the synchrony between mclk and fclk. and so, noticeable performance improvements can be had up to DDR4-4000, beyond which, you can still engage the divider to push mclk further up.
Sources:
VideoCardz, WCCFTech, Tecnopat
The first domain is fclk or Infinity Fabric clock. Each of the two CCDs (8-core CPU dies) has just one CCX (CPU core complex) with 8 cores, and hence the CCD's internal Infinity Fabric cedes relevance to the IFOP (Infinity Fabric over Package) interconnect that binds the two CCDs and the cIOD (client I/O controller die) together. The next frequency is uclk, or the internal frequency of the dual-channel DDR4 memory controller contained in the cIOD. And lastly, the mclk, or memory clock is the industry-standard DRAM frequency.
62 Comments on AMD Ryzen 5000 Series Features Three Synchronized Memory Clock Domains
@1usmus SAVE US ALL WITH A ZEN 3 DRAM CALCULATOR BY END OF YEAR PLEASE!!!! make a patreon dude, i'd gladly throw a fiver your way and im sure a lot of other people would too. MAKE THAT MONEY BUY A JACUZZI yeeeeeeeeeeeee
There are some timings that are exclusive to AMD or Intel, but the general know-how, important primaries/secondaries, and IC characteristics carry over between the two camps. B-die and Rev.E have been doing plenty of daily stable 4000MT/s+ in the more hardcore memory OCing Intel community; B-die in particular has been doing it since the 8th gen Intel days, since each generation of Skylake really only improves the memory controller (quite a bit, however). With good B-die, current Comet Lake users are regularly pushing rather close to DDR4-5000 stable, but it does require you to put in the work.
It's the ubiquitous Hynix that has me a bit more concerned, as even recently released "new" CJR/DJR kits generally top out a hair under DDR4-4000, since Hynix does start to struggle at that point with both raw frequency and voltage.
And I believe that DRAMcalc will probably need an update for the new 5000. But dont expect it to be updated upon Nov5th. These things need time...
this is it boys!!!! 4000 cas 15 for $160
mmmm Zen 3 will love that ram right there... I want it so bad... my mobo has QVL with it too... eeeek
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But this is just speculations for both cases. Time will tell...
Zen3 6 and 8-core chips probably won't get such a gain from FCLK increases since they'll have a single CCX that doesn't need to use the infinity fabric to communicate with any other CCXs
Any idea why that is, though? I'm no expert when it comes to memory controllers.
So with Ryzen, is 2 sticks better than 4? I know with Intel systems there isn't really an issue with 4 sticks and running high speeds and lower latency.
I work mine with 1.45VLess ranks is the right to say. 2 ranks are better than 4 in terms of OC and achieving high speeds. Less ranks = less load to UMC (mem cotroller).
Other than OC if used in stock, 4 ranks may give a slight advantage in performance against same spec sticks with 2 ranks overall.
The way ZEN2 is build it doesnt care too much for high speed memory past the 3200MHz point. Other than memory benchmarks you dont see/feel the difference.
AMD CPUs had the same issue (too much RAM voltage killed the CPU) pre 2010. I killed a Phenom CPU like that and instantly, not in long term.
At Zen2's launch there were LN2 overclockers pushing RAM speeds up well over 5GHz but in doing so they had to decouple the fabric clock (FCLK) and DDR4 clock. Yes, they set frequency records, but no it wasn't actually that much faster because doing so required a halving of the FCLK.
There's nothing to stop you from running DDR4-4666 in an X570 board right now - but nobody does it because although you get extra RAM bandwidth it genuinely doesn't do much for performance and is about as good as much, much cheaper DDR4-3600. If you are running some niche application that needs bandwidth, AM4 isn't the answer - you should just pony up for a Threadripper (or any other quad-channel platform).