Wednesday, June 9th 2021
Intel "Raptor Lake" is a 24-core (8 Big + 16 Little) Processor
Intel's strategy toward increasing CPU core counts could be to dial up the counts of smaller low-power CPU cores, according to a "Moore's Law is Dead" leak about the next-generation "Raptor Lake" mainstream processor. The chip is said to have 8 larger high-performance cores, and a whopping 16 low-power cores. The eight bigger performance cores will be "Raptor Cove," the successor to "Golden Cove," featuring higher IPC and more instruction sets, although the report only references this as an enhancement to "Golden Cove." The sixteen smaller low-power cores, however, are expected to remain "Gracemont," carried over from "Alder Lake-S." The "Raptor Lake-S" processor is slated for a Holiday 2022 release, and being touted as a competitor to AMD's "Zen 4" based desktop processor.
Sources:
Moore's Law is Dead (YouTube), VideoCardz
50 Comments on Intel "Raptor Lake" is a 24-core (8 Big + 16 Little) Processor
To programs (games) that dont use it, its useless hardware.
To programs that do use it (workstation stuff) it's a massive speed boost.
Some games are starting to use AVX, but its not common yet (and so many variants of AVX, they may use older standards than modern CPU support anyway)
It's better to have them and not need them than to not have them and crash an app, or make it perform like trash.
yuzu for example will run some games at 3FPS if FMA is missing, precision needs to be lowered to make old CPUs perform well.
But for a full blown gamer and/or workstation desktop. I would rather like to have fewer but powerful cores. So like 16 cores with smt/ht than like 24 cores and perhaps only 8 cores of them has sms/ht. Hence why I chose to go with a Ryzen 9 5950X and not wait for Intel's alder lake. 5950X seems beffer fitted for my needs.
So i have mixed feelings about this hybrid core thing. Some places it makes sense and in other areas it doesn't make so much sense.
Just think of it like having 8 cores at 4.5GHz and 16 cores at 3.9GHz where the 16 cores use as much power as the 8 faster ones. The missing instructions are rarely used ones which again stress the power generated by the CPU.
Even desktops are power bound, not maybe so strictly as notebooks but if you can generate a limited amount of heat than there are many situations where 16 low power cores can do more than 8 megacoreswithsquareballs (TM).
In the end it seems to be like: you got a 150W power ceiling (well, it is Intel ... 250W ... 300W...), you decide how to reach this power limit ... today it is 2 cores superfast or all cores somewhat fast in a dynamic manner ... tomorrow it will be decided when buying the CPU: 8 big and 8 small (average Joe) or 24 small (I do serious stuff) or 12 big (I am a gamer).
I am not so sure the big-little is such a winning idea though. Time will tell.
I don't need regular CPU + 1000 little calculator cores
Time will tell but Intel are baffling ATM.
This could be a big first step towards 3D stacked CPU's from Intel. In fact I feel Intel could stand to have a small, medium, big core type of arrangement with 3 or more core size types possibly even 4 in the not so distant future. In that scenario the best way to 3D stack them is in a pyramid structure you might invert it though and do like AMD has with ZEN 3+ with the structural silicone. It really depends honestly the biggest die might be a smallest cores, but the number of those cores is much higher while the smaller core might be a single core chip at the very top with very highest performance in mind.
They also shipped a stacked big core on some little cores to consumers, admittedly god knows who and where they're a bit unicorny.
Basically:
Normal add: x + y = z
AVX add:
x0 + y0 = z0
x1 + y1 = z1
x2 + y2 = z2
x3 + y3 = z3
x4 + y4 = z4
x5 + y5 = z5
x6 + y6 = z6
x7 + y7 = z7
x8 + y8 = z8
x9 + y9 = z9
x10 + y10 = z10
x11 + y11 = z11
x12 + y12 = z12
x13 + y13 = z13
x14 + y14 = z14
x15 + y15 = z15
AVX Fused multiply add:
x0 * y0 + z0 = w0
.
.
.
x15*y15 + z15 = w15
Current CPUs can execute ~3 AVX or 3 normal add instructions per cycle. So the 16X data points = 16X faster. Often the normal adds are just AVX adds, with only x0 + y0 = z0.
I guess expediting the transition this way is better.
Two or three small cores will get more work done per watt of power than one large core, and cm² of small cores will get more work done than a cm² of large cores - it's reasonable to expect that, right?
I mean, that's when AVX512 isn't used and with a workload that's highly multithreaded. If it isn't highly multithreaded then you don't need more than 8 SMT cores.
That would depend on the task , environment and other running applications but I can't see where your getting your ideology at all.
Highly multi threaded and low throughout per core is it's bow string.
They're saving those big cores for directed application battering ie games.
Intel will be touting
- the high frequency of the big cores
- the high performance in games thanks to those big cores
- the low power consumption thanks to the little cores
- the number of cores
And people will be buying the wagon with the 8 horses and the 16 dogs, thinking they are getting 24 horses, while AMD will be trying to sell a cart with "only" 16 horses.
TBH I'm not sure how this is going to work out.
With the luck they've had in recent memory I'm starting to think if this doesn't do too well it could blow back in their face like Bulldozer did for AMD. Intel can survive it more readily but at the same time every bit hurts just like it would help.
If Intel doesn't want to keep falling everyone here knows what they need to do but the big question is "how".
I'm not seeing this as being the way, it's more of a hybrid core setup that may have some advantages but I'm thinking it's also going to have more disadvantages than advantages.
However:
Doesn't mean it won't work either, this could well be a suprisingly good chip so let's see what happens before actually labeling it a failure.