Friday, December 10th 2021
AMD EPYC Genoa Processors to Feature Up to 12 TB of DDR5 Memory, Maximum Speeds of 5200 MT/s
Just yesterday, thanks to the Linux driver update, we found information stating that AMD's upcoming EPYC Genoa processor generation based on Zen 4 core IP will have a 12-channel memory controller. However, we didn't know how AMD engineered the memory controller of this processor generation and some of its maximum capabilities. However, there is an exciting discovery. According to the report from ComputerBase, with information exclusive to them, AMD will enable up to 12 TB of DDR5 memory spread across 12 memory channels. The processor supports DDR5-5200 memory, but when all 24 memory slots (two per channel) are populated, the DDR5 maximum speed drops to 4000 MT/s.
It is unclear why this is the case, and if any difficulties were designing the controller, so the maximum speed drops when every slot is used. One reassuring thing is that the bandwidth created by 12 memory channels should be sufficient to make up for the lost speed of DDR5 memory reduction.
Source:
ComputerBase.de
It is unclear why this is the case, and if any difficulties were designing the controller, so the maximum speed drops when every slot is used. One reassuring thing is that the bandwidth created by 12 memory channels should be sufficient to make up for the lost speed of DDR5 memory reduction.
20 Comments on AMD EPYC Genoa Processors to Feature Up to 12 TB of DDR5 Memory, Maximum Speeds of 5200 MT/s
But 12TB of RAM with the on die caches....
We all know that DDR5 modules are dual-channel limited to half the bandwidth of DDR4, so this "12-channel" MI is actually only 6-channel in reality..
As expected this is confusing, but it looks like everyone settled on calling the 64-bit (80-bit with ECC) DDR5 module a channel despite it being internally 2 independent 32- or 40-bit channels.
With the DDR5 performance is like the new intel chips, I wonder if it's going to be detrimental to the IPC.................I guess time will tell.
24 memory modules are 24x64-bit.
If 2 memory modules is 1 channel, then 1 channel is 4x32-bit.
So, for the memory module 1 channel is 32-bit.
While for the motherboard 1 channel is 128-bit.
Does make sense better now? :kookoo:
The current most common understanding is that one channel is 64 bits, and one half of that is often called a "subchannel". Very quick googling reveals that Micron, Kingston and MSI call it a subchannel, while Rambus calls it a channel.
128-bits? Not in any case. Motherboards of course support two modules per channel but that doesn't make the channel 128 bits wide; the two modules share the same 64-bit data bus.Had to dig it from the bottom of my brain ... there's a Genoa more closely linked to computers than a sandwich is: second.wiki/wiki/genoa_systems
New DDR5 SDRAM standard sees performance boost, dual-channel DIMM (techxplore.com)
The servers get 128-bit memory channel.
While the non-servers get 32-bit memory channel..
Likely for clarity of communication, it seems that platform holders, motherboard makers and others are using the term "channel" for DDR5 platforms and motherboards to mean "equivalent to previous DDR channels", i.e. the two 32-bit channels you'll find on a DDR5 DIMM are treated as "one". So that if you read about an 8-channel setup from a previous generation and this one you're reading about the same aggregate bandwidth, and not half.
This is technically inaccurate due to DDR5 splitting up the previous 64-bit channels, but other than on a technical level, that simply doesn't matter, and sticking to the technically accurate terminology either presupposes a bunch of knowledge that few people have (even among people making server purchase decisions), or necessitates a clarification that said channels are half width (otherwise they get sued for misleading marketing). Thus the technically accurate terminology is avoided outside of the relatively few scenarios where it makes sense.
What you're saying about 128-bit channels is just mixing up 1/2/3/4DPC layouts with these aggregate 64-bit channels. You can still have nDPC with DDR5, and this ultimately isn't affected by the splitting of the bus interface. Two DIMMs in a daisy-chain or T-topology layout will still have their channel(s) in common, just like previously.
To which CPU-Z disagrees.