Thursday, December 16th 2021
TSMC Announces the N4X Silicon Fabrication Process
TSMC today introduced its N4X process technology, tailored for the demanding workloads of high performance computing (HPC) products. N4X is the first of TSMC's HPC-focused technology offerings, representing ultimate performance and maximum clock frequencies in the 5-nanometer family. The "X" designation is reserved for TSMC technologies that are developed specifically for HPC products.
"HPC is now TSMC's fastest-growing business segment and we are proud to introduce N4X, the first in the 'X' lineage of our extreme performance semiconductor technologies," said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. "The demands of the HPC segment are unrelenting, and TSMC has not only tailored our 'X' semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric advanced packaging technologies to offer the best HPC platform."Leveraging its experience in 5 nm volume production, TSMC further enhanced its technology with features ideal for high performance computing products to create N4X. These features include:
For more information, visit this page.
"HPC is now TSMC's fastest-growing business segment and we are proud to introduce N4X, the first in the 'X' lineage of our extreme performance semiconductor technologies," said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. "The demands of the HPC segment are unrelenting, and TSMC has not only tailored our 'X' semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric advanced packaging technologies to offer the best HPC platform."Leveraging its experience in 5 nm volume production, TSMC further enhanced its technology with features ideal for high performance computing products to create N4X. These features include:
- Device design and structures optimized for high drive current and maximum frequency
- Back-end metal stack optimization for high-performance designs
- Super high density metal-insulator-metal capacitors for robust power delivery under extreme performance loads
- These HPC features will enable N4X to offer a performance boost of up to 15% over N5, or up to 4% over the even faster N4P at 1.2 volt. N4X can achieve drive voltages beyond 1.2 volt and deliver additional performance. Customers can also draw on the common design rules of the N5 process to accelerate the development of their N4X products. TSMC expects N4X to enter risk production by the first half of 2023.
For more information, visit this page.
15 Comments on TSMC Announces the N4X Silicon Fabrication Process
With that said, these are leading-edge packaging technologies, they've been developed with specific customers in mind and may include know-how from those customers. It's not like AMD's purchase manager called TSMC's sales manager and said, hey, we heard you have that, can we have some of it.
Other companies are getting on the chiplet train later than AMD. IBM seems to have been ready for it, NVidia has a bit of usage but not as much as I thought they'd have by now. AMD really went all in on chiplet designs: Zen1, Zen2, Zen3, MI200, etc. etc.
AMD didn't make the physical connections. They just rewrote their protocols to use such connections (aka: Infinity Fabric), which is still a major step forward... albeit a temporary one. (Now that chiplets are proven, everyone else is moving into the space, such as Intel)
They are using it to stack some cache. My thought is that this will be expensive, but we'll see.
www.game-debate.com/news/25012/tsmc-unveils-wafer-on-wafer-3d-stacked-silicon-that-could-double-gpu-core-count
And this concept isn't new (2010) :
www.nextbigfuture.com/2010/03/ibm-work-on-3d-chip-stacking-will-take.html
It's probably worth mentioning that the first 3D Stack product was 3D HBM on the Fury GPU. That was 6 years ago IIRC.
Also Intel Lakefield was a Foveros 3D chip.
So as far as 3D stacking, that's not new. Heat is the main problem, which is why you only see it on something like Lakefield or memory modules so far. Will be interesting to see if / how they solved that.
www.techpowerup.com/272489/intel-14-nm-node-compared-to-tsmcs-7-nm-node-using-scanning-electron-microscope