Tuesday, February 22nd 2022
AMD Details its 3D V-Cache Design at ISSCC
This week, the International Solid-State Circuits Conference is taking place online and during one of the sessions, AMD shared some more details of its 3D V-Cache design. The interesting part here is the overall design of AMD's 3D V-Cache, as well as how it interfaces with its CPU dies. The cache chip itself is said to measure 36 mm² and interfaces directly with the L3 cache using a Through Silicon Via or TSV interface. For all the CPU cores to be able to communicate with the 3D V-Cache, AMD has implemented a shared ring bus design at the L3 level. The entire L3 cache is said to be available to each of the cores, which should further help improve performance.
The 3D V-Cache is made up of multiple 8 MB "slices" which has a 1,024 contact interface with a single CPU core, for a total of 8,192 connections in total between the CCX and the 3D V-Cache. This allows for a bandwidth in excess of two terabyte per second, per slice, in full duplex mode. This should allow for full L3 speeds for the 3D V-Cache, despite the fact that it's not an integrated part of the CCX. AMD is also said to have improved the design of its CCX for the upcoming Ryzen 7 5800X3D in several ways to try and reduce the power draw, while improving clock speeds. AMD has yet to reveal a launch date for the Ryzen 7 5800X3D, but it'll be interesting to see if the 3D V-Cache and the various minor optimizations can make it competitive with Intel's Alder Lake CPUs until Zen 4 arrives.
Update: A few more slides from AMD's presentation have made their way online, which gives away some additional details. First and foremost, the SRAM used for the 3D V-Cache is manufactured by TSMC on the N7 node. AMD is referring to it as an "extended L3 Die" in the slides as well as a 64 MB L3 cache extension. The 3D V-Cache SRAM measures 41mm² and AMD has designed two additional structural supports of the CCD to help with thermal dissipation. To be able to fit everything into the same packaging as previous generation CPU's, AMD has had to thin the CCDs and L3 cache and the structural supports are also there to protect these thinned parts outside of the area covered by the 3D V-Cache.
Sources:
Hardware Luxx, @aschilling
The 3D V-Cache is made up of multiple 8 MB "slices" which has a 1,024 contact interface with a single CPU core, for a total of 8,192 connections in total between the CCX and the 3D V-Cache. This allows for a bandwidth in excess of two terabyte per second, per slice, in full duplex mode. This should allow for full L3 speeds for the 3D V-Cache, despite the fact that it's not an integrated part of the CCX. AMD is also said to have improved the design of its CCX for the upcoming Ryzen 7 5800X3D in several ways to try and reduce the power draw, while improving clock speeds. AMD has yet to reveal a launch date for the Ryzen 7 5800X3D, but it'll be interesting to see if the 3D V-Cache and the various minor optimizations can make it competitive with Intel's Alder Lake CPUs until Zen 4 arrives.
31 Comments on AMD Details its 3D V-Cache Design at ISSCC
At least for mainstream. Maybe on TR or EPYC it will be more commonly found.
MCM costs less than 3D V-Cache yet AMD is finding it hard to make it for the budget Ryzen 3 CPUs, sure they did it before but now they're thinking of making Ryzen 3 only as APUs (a single monolithic die) to reduce the costs of packaging.
This is not unusual though and we've seen this in plenty of chips in the past.
From the 5700g vs 5800x some games were the same and some had good benefits from the 32meg vs 16 meg cache.
Why go bashing in all the windows of your car and keying it before selling it, when you can sell it for more just as it is? Yeah, "you" being AMD here..
Using 8 core chiplets in 4 core CPU's isn't the reasonable thing to do. AMD will earn more money from that chiplet if it sits in a more expensive CPU.
Just imagine the price of a single chiplet, 4 core CPU, with a 8 chiplet, 64 core EPYC CPU. Hint: the latter cost more than eight times the price of the former. WAY more.
What did a Ryzen 3100 cost in the beginning? 110 Euro, one chiplet.
The cheapest 64 core EPYC I could find? 5400 Euro, or 675 per chiplet. 49 times more per CPU, and 6 times more per chiplet.
So it's probable that AMD makes more money from more expensive CPU's, even though EPYC most likely have higher manufacturing costs altogether.
Also, increasing the market share in the server world is considered important in the long run.
You don't have to like this, but it makes perfect sense as to why AMD does this. Add chip shortage and they have yet another reason.
Comparing the 5800X3D with non-existing budget CPU's doesn't make sense either, since the 5800X3D isn't a budget model.
I'm glad to read the clocks are capable of doing beyond 5Ghz. Thats just amazing, 8 core 16 thread with an additional 64MB of L3 cache. And the stock Ryzen 5800X was already "twice" as fast as a 2700X.
Great upgrade.
When is AMD releasing this thing?
It's like saying 16c is low end for gaming since you have threadrippers with 32 cores.Not bad. Wont have to wait for long :D