Thursday, August 4th 2022
Intel "Raptor Lake" Core i9-13900 De-lidded, Reveals a 23% Larger Die than Alder Lake
An Intel Core "Raptor Lake" engineering sample was de-lidded by Expreview giving us a first look at what will be Intel's last monolithic silicon client processor before the company switches over to chiplets, with its next-generation "Meteor Lake." The chip de-lidded here is the i9-13900, which maxes out the "Raptor Lake-S" die, in featuring all 8 "Raptor Cove" P-cores and 16 "Gracemont" E-cores physically present on the die, along with 36 MB of shared L3 cache, and an iGPU based on the Xe-LP graphics architecture.
The "Raptor Lake-S" silicon is built on the same Intel 7 (10 nm Enhanced SuperFin) silicon fabrication node as "Alder Lake-S." The "Raptor Lake-S" (8P+16E) die measures 23.8 mm x 10.8 mm, or 257 mm² in area, which is 49 mm² more than that of the "Alder Lake-S" (8P+8E) die (around 209 mm²). The larger die area comes from not just the two additional E-core clusters, but also larger L2 caches for the E-core clusters (4 MB vs. 2 MB), and larger L2 caches for the P-cores (2 MB vs. 1.25 MB); besides the larger shared L3 cache (36 MB vs. 30 MB). The "Raptor Cove" P-core itself could be slightly larger than its "Golden Cove" predecessor.
Even with the larger die, there's plenty of vacant fiberglass substrate inside the IHS. Future client sockets such as the LGA1800 have an identical package size to the LGA1700, with the additional pin-count coming from shrinking the "courtyard" in the land-grid (the central empty space). This indicates that future MCM chips such as the "Meteor Lake" have plenty of real-estate on the substrate, and Intel can maintain package-size and cooler-compatibility across several more generations. That said, "Raptor Lake-S" will be a Socket LGA1700 processor, will work with Intel 600-series and upcoming 700-series chipset motherboards; but will likely not be compatible with future LGA1800 platforms.
Sources:
Expreview (BiliBili), VideoCardz
The "Raptor Lake-S" silicon is built on the same Intel 7 (10 nm Enhanced SuperFin) silicon fabrication node as "Alder Lake-S." The "Raptor Lake-S" (8P+16E) die measures 23.8 mm x 10.8 mm, or 257 mm² in area, which is 49 mm² more than that of the "Alder Lake-S" (8P+8E) die (around 209 mm²). The larger die area comes from not just the two additional E-core clusters, but also larger L2 caches for the E-core clusters (4 MB vs. 2 MB), and larger L2 caches for the P-cores (2 MB vs. 1.25 MB); besides the larger shared L3 cache (36 MB vs. 30 MB). The "Raptor Cove" P-core itself could be slightly larger than its "Golden Cove" predecessor.
42 Comments on Intel "Raptor Lake" Core i9-13900 De-lidded, Reveals a 23% Larger Die than Alder Lake
Great for cooling, not great for cost
[SIZE=3][B]Intel "Raptor Lake" Core i9-13900 De-lidded, Reveals a 23% Larger Die than Alder Lake[/B][/SIZE]
The "Raptor Lake-S" silicon is built on the same Intel 7 (10 nm Enhanced SuperFin) silicon fabrication node as "Alder Lake-S."I was going to ask if it was being made on 14nm++++++++++ ;)
Intel is on an older node, their 10 nm is somehow equivalent to the TSMC 7nm that is costing around 10K if they have similar cost than TSMC, their CPU cost way less to make (around 75$). But we can't really assume that it cost the same. The fact that 10 nm was really late and had huge issue ramping up probably inflated the price quite a bit. But on the other side, TSMC have to make their profits on selling those wafer where intel make it's profit on selling the chips.
And one of the unknown is the actual defect density of both company. TSMC is actually having a better defect density than the value i used to keep things fair. (my point was to show that doing chiplet is very interesting for yield). With the actual defect density TSMC report on 5nm would have 408 good die of the I/O die per wafer and 764 good Zen 4 CCD.
In the end it's very had to compare and comparing margin is hard since a company selling more low end product will have lower margin. AMD have high margin but they are selling like hot cake in the datacenter market. It's also easy to understand why 10mn was so late. They probably had very bad defect rate that would have killed their production. Larger chips are more affected by worst yield than smaller chip. Just see how much more good I/O die AMD have by going from 0.2 defect rate to 0.09 versus the CCD.
But beyond cost, there is also capacity. If each company have 10k wafer per month, AMD will have been able to produce 3.5 millions CPU per month were Intel would only be able to produce 2.6 Millions. For top end desktop CPU at least. not sure what is the die size of the 13100/13400 family of CPUs
Even having 50% defective cores lets then use that CCX (which could still have four great cores leftover) in their budget lineup - and 1-2 dead cores lets dual CCX become a 5900x equivalent
In this regard it has exactly the same amount of future CPU generations available as intel: One
The only official word is that AMD says AM4 is not dead or discontinued, instead of doing one platform with DDR4 and DDR5, they're continuing both.
Whether that means more x3d chips (with the temperature and OCing issues fixed) or Zen4 based parts, we dont know.
15th sep, 2022 - Zen 4 launches (Link includes Z4 on AM4 rumour info)
Will it get higher end parts, or just refreshes like new APU's or something? We dunno. Bare minimum is they'll keep selling boards and some of the existing product stack.
But it's not intel, where 9 months after launch and its DOA
(11th gen, May '21 - 12th gen was released in feb '22 - and incompatible)
A combination of the two technologies could let AMD create some incredible hardware - With how Intel made MS patch windows, nothing is stopping 8 Zen4 3Dcache "P" cores as the primary CCX, with 24 Zen3 'E' cores (undervolted for efficiency, like at the 4.5GHz level) in another three CCXs
Do an intel, with some cores for single threaded performance and low ass 3Dcache latency, with more efficient last-gen ones to take over the multi threaded workloads, re-using older parts
Imagine the cost savings of using existing Zen 3 dies in hybrid Zen 4 parts, since they can be also be used in any product in the AM4 stack, with existing stock and a steady supply of parts on mature fab processes?
And then because they've already proven they can re-use an IO-Die between series, that technically could work on AM4 and AM5. (AM4 parts would simply need a 105W-140W limit)
Have they tested this stuff internally? Seems like it.
Will it get released? nobody knows :(
I'm not sure i worded part of that right, but the idea of AMD making Zen 3 parts for a few more years seems insanely cost effective as a business. Focus on a single 8 core CCX die, and making it as cheap and reliable as possible over time at the fab plants.
They could use them from anything from a 5600x to a Zen 4 hybrid, giving them almost no risk of mass producing them and stockpiling them.
It's not like intel where the E cores are something new, they could use the exact same CCX die on any AM4 or AM5 part they wanted, giving them financial loss if they cancel a product or end AM4 support
Even if theres failed cores on the dies, they can still do 5600x, 5900x or any hybrids that add 6 core CCX's - the cost efficiency is still there and will definitely be cheaper than any Zen4 CCX's, for a few years at least.