Friday, September 23rd 2022
NVIDIA AD103 and AD104 Chips Powering RTX 4080 Series Detailed
Here's our first look at the "AD103" and "AD104" chips powering the GeForce RTX 4080 16 GB and RTX 4080 12 GB, respectively, thanks to Ryan Smith from Anandtech. These are the second- and third-largest implementations of the GeForce "Ada" graphics architecture, with the "AD102" powering the RTX 4090 being the largest. Both chips are built on the same TSMC 4N (4 nm EUV) silicon fabrication process as the AD102, but are significantly distant from it in specifications. For example, the AD102 has a staggering 80 percent more number-crunching machinery than the AD103, and a 50 percent wider memory interface. The sheer numbers at play here, enable NVIDIA to carve out dozens of SKUs based on the three chips alone, before we're shown the mid-range "AD106" in the future.
The AD103 die measures 378.6 mm², significantly smaller than the 608 mm² of the AD102, and it reflects in a much lower transistor count of 45.9 billion. The chip physically features 80 streaming multiprocessors (SM), which work out to 10,240 CUDA cores, 320 Tensor cores, 80 RT cores, and 320 TMUs. The chip is endowed with a healthy ROP count of 112, and has a 256-bit wide GDDR6X memory interface. The AD104 is smaller still, with a die-size of 294.5 mm², a transistor count of 35.8 billion, 60 SM, 7,680 CUDA cores, 240 Tensor cores, 60 RT cores, 240 TMUs, and 80 ROPs. Ryan Smith says that the RTX 4080 12 GB maxes out the AD104, which means its memory interface is physically just 192-bit wide.
Sources:
Ryan Smith (Twitter), VideoCardz
The AD103 die measures 378.6 mm², significantly smaller than the 608 mm² of the AD102, and it reflects in a much lower transistor count of 45.9 billion. The chip physically features 80 streaming multiprocessors (SM), which work out to 10,240 CUDA cores, 320 Tensor cores, 80 RT cores, and 320 TMUs. The chip is endowed with a healthy ROP count of 112, and has a 256-bit wide GDDR6X memory interface. The AD104 is smaller still, with a die-size of 294.5 mm², a transistor count of 35.8 billion, 60 SM, 7,680 CUDA cores, 240 Tensor cores, 60 RT cores, 240 TMUs, and 80 ROPs. Ryan Smith says that the RTX 4080 12 GB maxes out the AD104, which means its memory interface is physically just 192-bit wide.
152 Comments on NVIDIA AD103 and AD104 Chips Powering RTX 4080 Series Detailed
In power draw/TDP we already know that it will win by a considerable margin. Now we need to know the performance :P
This sucks, but press has to abide to those things for the better good
The only thing I'd moan about for now is the costs....
Nvidia makes the confusion, not the press.
If the press cause more confusion,. Good it might make buyer's think more before purchasing.
A 104 die is not a X80 card GPU over nvidia's entire life span until today.
At the same time, RTX 4080_12 and AD104 have got same CUDA core count - 7 680.
RTX 3080 Story:
1. RTX 3080_10 - GA102-200 => 8 704 CUDA cores (320bit);
2. RTX 3080_Ti - GA102-225 => 10 240 CUDA cores (384bit);
3. RTX 3080_12 - GA102-220 => 8 960 CUDA cores (384bit).
So, they hold GA102-220 for later release.
RTX 3090 Story:
1. RTX 3090 - GA102-300 => 10 496 CUDA cores (384bit);
2. RTX 3090_Ti - GA102-350 => 10 752 CUDA cores (384bit).
No part of it was Afaik.
The name is the last important part fallow by memory bus.
Who cares if its 102, 103, 104, or 42069? What matters is the perf/$, not the codename of the hip itself.
I wonder how well the GPU would work without it, Unlike RDNA2, RDNA3 Flagship will have huge bandwidth to play with.
According to rumors Navi31 will be only 12% smaller than AD102.
Navi 32 will be only -9% from AD103.
You are probably comparing only the compute chiplet with AD103!
But in performance/Watt RDNA3 will be better but not by much, it all depends from the TDP that AMD will target! (If you undervolt also 4090 and target 350W for example, probably they will have very close performance/Watt!
At 7nm 128MB infinity cache was around 78mm², so 96MB around 58.5mm².At 6nm with the same T libraries it would be around 51mm²-54mm² or at this ballpark.
Even if they targeted much higher throughput using higher T libraries, I don't see them more than double from that, so 108mm² at max.
The die area of the chiplets in Navi31 will be according to rumors 225mm² at least, so what you're saying doesn't add up imo.