Wednesday, July 19th 2023
Next-gen AM5 Motherboard Platforms Could Support USB4
AMD's CEO Lisa Su is reported to be visiting a number of companies in Taiwan this week—one of her objectives seems to be getting next generation AM5 desktop platforms prepped with USB4 support. Hardware news site MyDrivers believes that Asmedia played host to Team Red's leader at some point—this is a significant development given that this Taiwanese company specializes in making motherboard chipsets and USB controllers, although Su has allegedly met with other competing firms. Asmedia is reported to be a market leader in terms of implementing the latest USB4 tech, with certification awarded by the USB-IF Association.
Prior leaks have implied that the two companies are already involved with each other on a separate project—their collective goal being Thunderbolt 4 support on next-gen AMD platforms. The timing of this trip to Taiwan suggests that forthcoming AM5 motherboards offering USB4 support could be lined up for launch next year, alongside the "Zen 5" Ryzen 8000 CPU series. Boards based on current gen A620, B650 and X670 chipsets could be refreshed with the latest USB connectivity standard.
Sources:
My Drivers, Wccftech
Prior leaks have implied that the two companies are already involved with each other on a separate project—their collective goal being Thunderbolt 4 support on next-gen AMD platforms. The timing of this trip to Taiwan suggests that forthcoming AM5 motherboards offering USB4 support could be lined up for launch next year, alongside the "Zen 5" Ryzen 8000 CPU series. Boards based on current gen A620, B650 and X670 chipsets could be refreshed with the latest USB connectivity standard.
121 Comments on Next-gen AM5 Motherboard Platforms Could Support USB4
It is also a very obvious step forward, NOT supporting USB4 on the next AMD platform (chipset) would be a serious mistake on AMD's part, even though very few people will actually make use of it. Any new technology is always a real marketing tool as it WILL be highlighted, and tested when the platform arrives. However, it's cost will be part of the descision, as always.
"If" AMD's next "chipsets" follow the same concept as the first AM5 chipsets then we will see two chips, the full one, and a cut-down one, and then they can use two of the full chips to produce three market segments whilst still only designing, producing and supporting a single piece of silicon. If so, it wound IMHO be insane for AMD to not support USB4 on the middle chipset (B750 assumed), and to drop it on the budget option.!
Whether or not AMD decides to bake USB4 into the CPU silicon itself is a separate question from the chipset is not a question, the question "when", and when in what market segments.?
However, I'm not sure if the information is reliable, the exact pin configuration may be confidential information and published info may be just a guess.
If AMD was smart, and not run by a**holes, they would give out more PCIe 4.0 lanes instead of fewer PCIe 5.0 lanes. But corporate greed is an amazing thing.
Most people don't have a 10Gb/s connection of any kind, and most people around the world don't even have a 1GB/s internet connection. The vast minority of people have a NAS network.
Most people don't need and won't utilize a USB4 connection. The general consumer still buys mostly garbage USB3 thumb drives that more often than not run at USB 2.0 speeds.
Would both be nice? Sure, but the cheap motherboards are cheap for a reason, and it's because they don't have (and won't have) 10Gb/s and USB4.
Technological progression means getting MORE for LESS, not LESS for MORE. Back in the Athlon 64 days, dual x16 PCIe slots were the norm on high-end boards. Then Intel introduced X99 and the HEDT segmentation nonsense, then started hiking HEDT prices to the point where nobody is willing to pay for it just to get a decent number of PCIe lanes, which caused HEDT to start dying, which pushed prices up even further. And since AMD apparently has no better marketing strategy than "copy Intel by ripping people off", their own HEDT platform is similarly dying.
Dual full-length x16 PCIe slots with 24 lanes between them is all I'm asking for, AMD and motherboard manufacturers. I'm not even asking for 16+16 lanes, just 24! And guess what, Zen 4 already offers 24 lanes of PCIe 5.0, except the 8 lanes of so-called "general purpose" are ALWAYS allocated to M.2 SSD slots, even if those slots aren't populated.
Why can't we instead ALLOCATE THOSE LANES TO THE SECOND PCIe SLOT BY DEFAULT and as M.2 SSDs are plugged in, that slot LOSES lanes? Like how AM4 worked?
Or, since each chipset ITSELF puts out 8, again "general purpose" lanes, why not assign THOSE to the second PCIe slot? They're "only" PCIe 4.0 lanes but the bandwidth honestly doesn't matter, the lane count does.
This isn't rocket science and it isn't an unreasonable request. It does, however, require AMD and motherboard manufacturers to pull their collective finger out and THINK anout what is GOOD and USEFUL for customers, then actually implement the same. Rather than 20 M.2 SSD slots or RGB bright enough to eclipse the Sun or any one of the other completely useless "features" that have fallen out of a marketer's anus, just GIVE US OUR PCIe SLOTS BACK.
Maybe what I have isn't truly USB4 and was lied to? Or maybe they are talking about native USB4 support for all mobos opposed to just a few? Maybe it means it will be part of the CPU lanes opposed to the mobo? Or maybe USB4 speeds are actually much faster than what the USB4 on the current AM5 motherboards offer.
Can anybody clarify this as I was actually planning on buying the USB4 device this weekend to use. This is all news to me and I read tech stuff all throughout the day.
you have a build in controller,
anybody can install usb4 controller at an expense of 4x pcie lanes.
:rolleyes::roll:
USB4 is new-ish, we'll probably see it in AM6, we may see low end motherboards with USB4 for AM6, as I'd expect the I/O controller on the CPU to support it. It would be down to motherboard makers to decide whether or not it's worth the cost of actually putting it on the board rather than additional USB3/3.2 ports.
As for 10Gb/s ports, we may see it on mid-range motherboards on AM6, as many AM5 boards in the mid-range are already replacing the 1Gb/s with 2.5Gb/s. 10Gb/s still remains niche though, so I don't expect the demand for it to grow all that fast. Most residencies around the world can't even obtain faster than 1Gb/s connections right now, and the utility of downloading 100GB in a few seconds for the average consumer is... limited.
It's entirely possible to get USB4 support on current-gen AM5 boards by using an add-on controller, which as @M440 noted is what your motherboard does:
- 2 x USB4® ports with Intel® JHL8540 USB4®
The tradeoff is that add-on controllers consume valuable PCIe lanes that could better be utilised for other connectivity. You're fine.Board vendors are also free to wire the chipset independently, without daisy-chaining. I have not heard anywhere that AMD does not allow this configuration. Intel's TB chip uses only four PCIe 3.0 lanes. That's almost nothing, especially when there is PCIe switch chip available or when the chip can be wired either on the chipset or on CPU. Let's not split hair in half where not necessary.
I agree that PCIe Gen5 was deployed too early, but switch chips can easily be used to provide variable connectivity. Several boards do have those switch chips, especially Z790 boards that allocate x8 link from GPU for Gen5 NVMe drives.
PCIe switches are not as popular anymore, but that does not mean that board vendors cannot be encouraged or influenced to use them more.
Look at the diagram I posted and do not spread falsehoods regarding the number of PCIe lanes from CPU.
24 Gen5 lanes are offered by CPU for PCIe connectivity, x16 (or x8/x8) for GPU/AIC, and two x4 links for NVMe drives.
Again, motherboard vendors are free to install PCIe switch chip between CPU and other slots that can effectively double the number of lanes into 48 Gen4 lanes. It's up to them.
Two x16 slots can easily be designed to run in x16 Gen4 mode, if electrically wired and have PCIe switch chip sitting atop.
Also, quad AIC with four NVMe drives can run in x8 Gen5 slot in x16 Gen4 mode if AIC vendor installs PCIe switch chip on the AIC itself. Two Gen5 lanes can be configured to serve each Gen4 NVMe drive at it full speed. I don't see the issue here. If quad drive AIC has x8 Gen5 link, each drive could be accessed individually IF AIC vendor installs PCIe switch chip on the AIC itself to provide x4 Gen4 link to each drive. I don't see a problem. This is nonsense too. It's up to motherboard vendors to use available lanes creatively. With 24 Gen5 lanes, a lot of stuff is achievable with PCIe switch chip. You can double Gen4 lanes, you can quadruple Gen3 lanes, etc. Plenty of stuff is possible. This does not make sense. Motherboard vendors and AIC vendors are responsible for designing boards and peripherals that can creatively use available 24 Gen5 lanes. You can have two time Gen4 lanes and four times Gen3 lanes from CPU with PCIe switch chip without losing bandwidth.
For 10GbE NIC you just need two Gen3 lanes from the chipset. Where is the problem? What exactly is "pathetic" and "anemic"? Perhaps imagination of board vendor engineers? It is up to proponents of the idea that we need more and faster connectivity to provide such evidence in order to convince tech industry that such need is indeed present. Simple. If AsMedia USB4 chip is robust and finally in full working condition, AMD does not need to integrate it on desktop CPU. We don't know what talks were in the background. I am curious whether there is enough space on Zen5 silicon to add two USB4 controllers. It'd be good to find out. Whatever the case, native USB4 will be there in next iteration, discrete or integrated. Also, do not forget that there is USB4 20 Gbps (Gen 2x2) and USB4 40 Gbps (Gen 3x2).
The only thing is waste of x4 Gen5 link, as each chipset is x4 Gen4.
You have 28 lanes in total on CPU: x16 link for GPU, x4 for NVMe drive and another x4 and x4 can link one chipset each.
I have not seen any documentation stating that this is not allowed and that daisy-chaining is the only way. Have you?