Friday, August 23rd 2024
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AMD Ryzen 9000X3D Processors with 3D V-Cache Arrive in January at CES 2025
AMD's upcoming Ryzen 9000X3D series of processors with 3D V-Cache have been reportedly scheduled to arrive in January 2025 and should make a debut at the CES event, a few months later than initially expected. While disappointing for eager enthusiasts, the delay could signify that AMD is taking extra precautions to ensure a smooth launch and deliver a product that meets the high-performance standards set by its previous 3D V-Cache offerings. Delaying the new product launch could also be a strategic move by AMD to avoid potential supply chain issues or to align the launch with other product announcements.
We previously reported that the series will maintain the same cache size configurations as the last generation with 3D V-Cache, and it will just be an upgrade to up the performance of the new Zen 5 design. The launch of the 9000X3D series follows a smaller six-month gap from the regular Ryzen 9000 series, where the previous Ryzen 7000X3D and 5000X3D followed seven and seventeen months after the launch of their regular SKUs, respectively.
Sources:
HXL, via VideoCardz
We previously reported that the series will maintain the same cache size configurations as the last generation with 3D V-Cache, and it will just be an upgrade to up the performance of the new Zen 5 design. The launch of the 9000X3D series follows a smaller six-month gap from the regular Ryzen 9000 series, where the previous Ryzen 7000X3D and 5000X3D followed seven and seventeen months after the launch of their regular SKUs, respectively.
81 Comments on AMD Ryzen 9000X3D Processors with 3D V-Cache Arrive in January at CES 2025
www.techpowerup.com/forums/threads/amd-ryzen-9000x3d-processors-with-3d-v-cache-arrive-in-january-at-ces-2025.325881/post-5316501
When you can't increase the frequency much anymore, offer a large CACHE (i.e. 9800X3D) and the low hanging fruit for x86 code is mostly gone there's not a lot you can do except minor tweaks.
There are also a lot of SECURITY issues that come into play if you try to add in branch prediction or whatever that has the potential to increase performance.
SOFTWARE is where the big gains need to be made. I'm baffled why, in 2024, we're still having single-thread issues. Why isn't the RENDER thread or whatever the bottleneck is multi-threaded better? I honestly don't know as I have only a small amount of programming skills, but we got a little bit if improvement with DX11 and then supposedly DX12 was going to come along and solve this. But here we are. I've got a 12-core Ryzen R9-3900x but a modern 6-core is sometimes 2x as fast because of single core/thread bottlenecking.
:toast:
4/2023 7800X3D is going to age like fine wine. PBO, SMT off in some titles and now windows updates to improve over vanilla performance. Oh wait that was Zen5 marketing strategy.
The bigger question is now if Intel Arrow Lake brings competition this fall.
But did the 7800x3D also get a boost? New video soon?
Now what, Copilot+ or no Ryzen boost, so sad :(
Based on AM4 and 5800X3D performance I can see Amd making zen6 very competitive. AMD stagnates performance with Zen5 makes a big bang with zen6. It's plausible.
Maybe a touch better improvement with the X3D, perhaps 10% gains. If Intels next gen fails to strike a blow, AMD will see no reason to offer anything substantially better. I just hope, if there are limitations at the hardware level, AMD doesn't end up piercing and clawing for some added perf with opportunistic voltage profiles for potentially another set of early adopter burners.
The 7800X3D was around 20% faster over the 5800X3D. I'm not confident with seeing the same with 9000-series. Anyway doesn't bother me, i'm on a 5800X3D and mostly GPU limited.
TL,DR: Don't assume that AMD's engineers didn't consider several different designs and chose the most cost-effective one.
Keeping relatively small and separate dies (cores/IO) can improve wafer yields vastly and also you have the scalability to put together many different number of dies on package + you can cheap out on IOD as you dont need the last state of the art lithography for that one.
Tho I believe that if the uncore part is on die right next to cores a lot of things improve but then you loose all the above.
Its a trade off that AMD has chosen. Simple as that.
What we need, in my opinion, is an improved IF (something like Intel's tiles, or the Navi 31-32 interposer), and better CCD placement (closer to the centre of the package).
Strix Halo is for me the most interesting chip from AMD in the last 3-5 years, especially seeing how Strix Point performed!
Agree on the rest...
Faster interconnect is needed and AMD will improve at some point... The could've done it now with Zen5 but again they chose not to.
I think they will get away eventually with this one after X3Ds and many optimizations that will probably come.
But I dont see Zen6 to able to operate well enough if IOD and FCLK/UCLK staying same.
At least FCLK needs to gain like +50% or even x2 from current speed
Cant imagine though how would this affect power if they keep using same type of interconnection.
Probably they will introduce a more advanced one that higher speed will not draw much more power.
I cant comment further cause Im lacking knowledge on the subject.
Core+SoC combined can go down to <20W but there is still another 15~20W "lost" somewhere...
Single CCD CPUs will have Core+SoC lower because of lower SoC (~10W) power but still its not that PPT will drop to <20W
Here is 5600x, 7700x, 7900x and 9700x PPT and Core+SoC with higher RAM frequency.
(Just random screenshots from my library)
Zen 6 is your next upgrade. You make iitsounds like AMD is sandbagging on purpose which I don't believe is the case here.
Zen 5 and specifically turin looks like it was designed for Datacenter more so than client desktop. So it will excel in that area and looks to be just average on client desktop. I also believe the IOD and lack of memory bandwidth hurts it more than it will on server which doesn't have those bottlenecks.
docs.amd.com/r/en-US/ug1099-bga-device-design-rules/Power-Delivery-to-the-FPGA