Friday, August 23rd 2024
AMD Ryzen 9000X3D Processors with 3D V-Cache Arrive in January at CES 2025
AMD's upcoming Ryzen 9000X3D series of processors with 3D V-Cache have been reportedly scheduled to arrive in January 2025 and should make a debut at the CES event, a few months later than initially expected. While disappointing for eager enthusiasts, the delay could signify that AMD is taking extra precautions to ensure a smooth launch and deliver a product that meets the high-performance standards set by its previous 3D V-Cache offerings. Delaying the new product launch could also be a strategic move by AMD to avoid potential supply chain issues or to align the launch with other product announcements.
We previously reported that the series will maintain the same cache size configurations as the last generation with 3D V-Cache, and it will just be an upgrade to up the performance of the new Zen 5 design. The launch of the 9000X3D series follows a smaller six-month gap from the regular Ryzen 9000 series, where the previous Ryzen 7000X3D and 5000X3D followed seven and seventeen months after the launch of their regular SKUs, respectively.
Sources:
HXL, via VideoCardz
We previously reported that the series will maintain the same cache size configurations as the last generation with 3D V-Cache, and it will just be an upgrade to up the performance of the new Zen 5 design. The launch of the 9000X3D series follows a smaller six-month gap from the regular Ryzen 9000 series, where the previous Ryzen 7000X3D and 5000X3D followed seven and seventeen months after the launch of their regular SKUs, respectively.
84 Comments on AMD Ryzen 9000X3D Processors with 3D V-Cache Arrive in January at CES 2025
Its not that they have too many degrees of freedom, quite the contrary.
The gap between the IOD and CCDs is surprisingly large but the IFOP link is wide too. 128 bits per direction per link, or is it more? Diagrams like this one(Zen 3) do show, in part, why there's such a gap. That gap is significantly smaller in Epycs (but we don't know the number of layers on substrate).
Also in Zen 4, AMD moved the IOD closer to the centre, and the CCDs closer to the edge, by 1.6 mm (as measured by der8auer). That's weird.
Another hard to explain design decision is the orientation. The CCDs are the closest to the PCIe slots and away from the VRMs, even though they consume most of the power. The IOD is closest to the VRMs and away from the PCIe slots, even though all PCIe and other signals run from it. My naive EE mind tends to think that this causes many problems with space constraints and interference because too many power and signal wires have to run over each other on the substrate.
Steeve from GN said that Woligroski is not making things up, and that has information from unofficial channels that some key changes are at place.
If the vague hints are more than just optimism then everyone wins. Well, everyone except Intel.