Wednesday, November 13th 2024
AMD Unveils the Versal Premium Series Gen 2 Adaptive SoC (FPGA) with PCIe 6.0 and CXL 3.1 For Next-Gen, I/O Rich Applications
AMD on Tuesday released its flagship FPGA series, and possibly its most important product launch after the company's Xilinx acquisition, the Versal Premium Series Gen 2 SoC. It's hard to call this an FPGA, much in the same way as it's hard to call a modern processor "a CPU," there are many integrated devices, platform interfaces, and application-specific accelerators, and much in the same way, the Versal Premium Series Gen 2 is marketed as an "adaptive SoC," rather than a really powerful FPGA. Speaking of I/O, this is AMD's first product to implement PCI-Express Gen 6 and CXL 3.1.
There's no host platform that currently support these standards—neither EPYC "Turin" nor Xeon 6 "Granite Rapids," but it goes to show that the chip is future-ready and can put the new I/O standards to use. The chip is designed to be implemented as a standalone SoC, and so it supports both DDR5 RDIMMs and LPDDR5X, giving end-users the flexibility to go with the two vastly different memory standards depending on what their application is. These capabilities make the Versal Premium Series Gen 2 well-suited for demanding applications in sectors like data centers, communications, test and measurement, aerospace, and defense, where high-speed data processing is critical.
The main feature of the Versal Premium Series Gen 2 is its FPGA. Put short, think of an FPGA as a sea of transistors that you can program to work like any logic device you want. This is different from emulation, because the FPGA performs close to what an ASIC would. FPGAs are crucial when designing and prototyping ASICs, or for hardware manufacturers that have a very small production target to create the logic device they want using an FPGA (think a space agency creating an SoC for one of its interplanetary probes). The Versal Premium Series Gen 2, depending on the model, comes with anywhere between 1.40 to 3.27 million system logic cells (SLCs), 643k to 1.49 million LUTs, 3,320 to 7,616 DSP engines, 4 to 8 DDR5/LPDDR5x memory controllers, and a memory bus width ranging from 128-bit to 256-bit. I/O includes a dual PCI-Express 6.0 x8 interface (64 Gbps per lane), which converts to a CXL 3.1 interface of comparable bandwidth, and a multitude of MACs, including a 100 Gbps multirate Ethernet MAC, up to five 600 Gbps Ethernet MACs depending on the model, and a 400 Gbps high-speed crypto engine.
In addition to faster connectivity, Versal Premium Series Gen 2 includes enhanced security features. It is the first FPGA to integrate PCIe Integrity and Data Encryption (IDE) directly within its hard IP, offering high-level security for data in transit. It also incorporates 400 Gbps Crypto Engines, which support accelerated, secure data transmission. AMD has embedded encryption into the platform's DDR memory controllers, ensuring data at rest is also protected. Development tools for the Versal Premium Gen 2 will be available in 2025, with production expected in 2026. With these innovations, AMD's Versal Premium Series Gen 2 aims to redefine adaptive computing for industries seeking scalable, high-performance, and secure data handling solutions.
AMD will begin sampling and releasing development tools of the Versal Premium Series Gen 2 in 2025, while taking orders. Production of the SoC should commence in 2026—now you know why it comes with a PCIe Gen 6 interface.
For more information, visit the product page.
The complete slide-deck from AMD follows.
There's no host platform that currently support these standards—neither EPYC "Turin" nor Xeon 6 "Granite Rapids," but it goes to show that the chip is future-ready and can put the new I/O standards to use. The chip is designed to be implemented as a standalone SoC, and so it supports both DDR5 RDIMMs and LPDDR5X, giving end-users the flexibility to go with the two vastly different memory standards depending on what their application is. These capabilities make the Versal Premium Series Gen 2 well-suited for demanding applications in sectors like data centers, communications, test and measurement, aerospace, and defense, where high-speed data processing is critical.
In addition to faster connectivity, Versal Premium Series Gen 2 includes enhanced security features. It is the first FPGA to integrate PCIe Integrity and Data Encryption (IDE) directly within its hard IP, offering high-level security for data in transit. It also incorporates 400 Gbps Crypto Engines, which support accelerated, secure data transmission. AMD has embedded encryption into the platform's DDR memory controllers, ensuring data at rest is also protected. Development tools for the Versal Premium Gen 2 will be available in 2025, with production expected in 2026. With these innovations, AMD's Versal Premium Series Gen 2 aims to redefine adaptive computing for industries seeking scalable, high-performance, and secure data handling solutions.
AMD will begin sampling and releasing development tools of the Versal Premium Series Gen 2 in 2025, while taking orders. Production of the SoC should commence in 2026—now you know why it comes with a PCIe Gen 6 interface.
For more information, visit the product page.
The complete slide-deck from AMD follows.
16 Comments on AMD Unveils the Versal Premium Series Gen 2 Adaptive SoC (FPGA) with PCIe 6.0 and CXL 3.1 For Next-Gen, I/O Rich Applications
Their naming conventions are simply....ughhh
-continues reading-
Oh...it's a late 2025 sampling with late 2026 release of actual hardware. This stuff is two years out, and it's rather squarely focused on data center applications instead of making stuff like NPUs obsolete because an FPGA can be flashed to do anything great instead of having to have multiple co-processors who are dead space unless their unique functions are being used. This is a lot less exciting for consumers in the next 5-6 years...which is about how long the tech will require to trickle down. Sigh.
These aren't very relevant for PC or gaming enthusiasts, but their usefulness for makers and hardware hackers is undeniable for those with the skill to use them.
1) An FPGA is a field programmable gate array. My interest here is that you could image a processor onto the thing. Think not having to have ray-trace features take up space in your GPU, should you not enable them.
2) Speaking of why this matters for gaming...and the obvious fun for makers, imagine having a locked AMD image for about half a dozen configurations that AMD could tweak for each game. Very heavy on developmental features, but if they made their general performance values available developers could target to have specific features at specific levels enabled and disabled based on series. Think something along the lines of a slider in a game telling the FPGA to make a GPU that excels with the desired settings, no matter how big or small it is.
3) My limited time using FPGAs was focused on garbage software and performance generations old. If AMD is serious about this, and they support it with even a little bit of their open source initiative, I see a beautiful future where you emulate processors with a license, and a single piece of hardware can be your physics processor, NPU, or Raspberry-PI killer based only on whatever you plug into it.
4) FPGAs are not meant to be CPUs. They are meant to be a breadboard to make your own custom gate arrangement. By definition a CPU, like any processor, is a gate arrangement. I say this because an FPGA is the processor that you don't have to have lithography for...which makes it both the most flexible and least efficient (space wise) option. I choose to ignore the obvious downsides because most of them are imposed by having worse processes and poor support, whereas most CPUs are good at whatever they were designed and priced for.
I just have high hopes because, assuming the security is good, this is the future where you can download a licensed image to make the best processor for whatever it is you are doing...which means stuff like the GPU crypto craze will disappear under simply wanting to buy a literal chunk of silicon. Bigger silicon = more gates = better processors...so we don't get situations where artificial limiters determine wild swings in pricing. That may sound idealistic, but I also believe that if we could link this together then there would be less e-waste and you could patch out vulnerabilities by literally rebuilding every single one in existence with a software patch...which makes issues like Intel and AMD have with security due to predictive algorithms disappear without having to significantly reset hardware expectations. Again, dreaming more than a little. That said, having dreams is occasionally nice.
It's a product naming scheme meant to confuse the consumer, and is quite honestly just ugly and difficult to not laugh at over its obtuseness.
"Licensable IP cores" are pretty standard in FPGA development, and some of the basic ones (or ones that use chip specific functions) are freely available from the FPGA vendor and others, but the cutting edge stuff is all expensive since it's generally based on companies using them in their designs. They're not designed around or priced per unit. I'd be great if this changed, but it'd require a major overhaul in all sorts of software.
As it stands FPGAs are beyond the skills of even most makers to make use of, let alone gamers. There's continuous work to make them more approachable, but beyond throwing a premade bitstream on a chip in an FPGA based "emulator" there's an incredibly steep learnig curve. FPGAs haven't had their "Arduino" moment yet.