Thursday, December 5th 2024
Intel 18A Process Node Clocks an Abysmal 10% Yield: Report
In case you're wondering why Intel went with TSMC 3 nm to build the Compute tile of its "Arrow Lake" processor, and the SoC tile of "Lunar Lake," instead of Intel 3, or even Intel 20A, perhaps there's more to the recent story about Broadcom voicing its disappointment in the Intel 18A foundry node. The September 2024 report didn't specify a number to what yields on the Intel 18A node looked like to spook Broadcom, but we now have some idea as to just how bad things are. Korean publication Chosun, which tracks developments in the electronics and ICT industries, reports that yields on the Intel 18A foundry node stand at an abysmal 10%, making it unfit for mass-production. Broadcom validated Intel 18A as it was prospecting a cutting-edge node for its high-bandwidth network processors.
The report also hints that Intel's in-house foundry nodes going off the rails could be an important event leading up to the company's Board letting go of former CEO Pat Gelsinger, as huge 2nd order effects will be felt across the company's entire product stack in development. For example, company roadmaps put the company's next-generation "Clearwater Forest" server processor, slated for 2025, as being designed for the Intel 18A node. Unless Intel Foundry can pull a miracle, an effort must be underway to redesign the chip for whichever TSMC node is considered cutting-edge in 2025.
Sources:
Chosun, Reuters, Notebookcheck
The report also hints that Intel's in-house foundry nodes going off the rails could be an important event leading up to the company's Board letting go of former CEO Pat Gelsinger, as huge 2nd order effects will be felt across the company's entire product stack in development. For example, company roadmaps put the company's next-generation "Clearwater Forest" server processor, slated for 2025, as being designed for the Intel 18A node. Unless Intel Foundry can pull a miracle, an effort must be underway to redesign the chip for whichever TSMC node is considered cutting-edge in 2025.
90 Comments on Intel 18A Process Node Clocks an Abysmal 10% Yield: Report
Finally, Ian Cutress joined in and pointed out that the 8% 'yield' is 65% yield for a smartphone sized SoC - noting that TPU doesn't know what 'yield' means.
And as far as TSMC vs Intel, apples to apples tests winds up being 99% vs 60%, i.e. this:
And this is, folks, why I don't trust rumours. Someone says something extremely negative about intel, then someone else says something extremely positive 5 seconds later about the same company.
For something more normal, albeit still large - like Panther Lake - the yield is calculated to be 60%. Yield depends on the size of the chip.
This is a pretty basic error, and one which has TPU being called the "Mainstream Media" of tech. That is not a compliment.
They really should have retracted or amended their story.
If Intel's lithography yield is not too low, why did Intel contract TSMC to manufacture the compute die for its new CPUs?
When people team up to punish shorters and start to buy a lot of low prices stock that are used for shorting, stock price raises and shorters loose millions. And that particular stock gets suspended, lol.
Look at MSFT stock and compare it to shitty quality products they deliver. Windows 11 is still bug festival 3 years after release. Stocks are not about real value of the company. See AI stocks, it's all bullshit.Why we don't hear any news regarding good yields from Intel itself is a question in place.
Arrow Lake came out in October. As a rule of thumb the actual manufacturing of the dies used started 6 months to a year before that. Preceded by another year or so of preparations. The time frames vary by a lot but all this takes quite a long time. Pretty sure a year or two ago Intel was not sure what was going to happen to 20A or 18A so they were hedging their bets this time around.
And now AMD is not being as aggressive with Intel to it can get out of this crisis.
What I will say is that no matter if BSPDN worked on Intel 4. Given the improvements, that should have probably gone into 3N if it was as ready as they said.
I also think there should be some downstream consequences from flipping the chip, when you're dealing with actual products rather than tests. Tests will run at whatever, actual chips will be at 125-500W that will be now impossible to dissipate.
Hopefully, at least 2025 will bring mobile chips in a decent shape.