Monday, January 6th 2025

AMD Launches Ryzen 9 9000X3D Series "Zen 5" Desktop Processors with 3D V-Cache

AMD today expanded its Ryzen 9000X3D line of Socket AM5 desktop processors that combine the "Zen 5" microarchitecture with 3D V-Cache technology, with the introduction of two high core-count models, the Ryzen 9 9950X3D and the Ryzen 9 9900X3D. The 9950X3D is a 16-core/32-thread chip, while the 9900X3D is 12-core/24-thread. These are dual-CCD processors, and much like the Ryzen 9 7000X3D, the 3D V-Cache is only present on one of the two CCDs, while the other is a regular CCD with just the 32 MB on-die L3 cache. There is one key difference, though. Since AMD has redesigned 3D V-Cache for "Zen 5" to be below the CCD and not above, the CCD with it has the same clock speed boosting characteristics as the CCD without 3D V-Cache; and AMD has worked to refine its software-based OS scheduler optimization such that productivity applications favor either of the CCDs, while games stick to the one with 3D V-Cache.

The Ryzen 9 9950X3D comes with a base frequency of 4.30 GHz, and boosts up to 5.70 GHz, with a 170 W TDP. This is much higher than the 5.20 GHz maximum boost frequency of the Ryzen 7 9800X3D, which makes the 9950X3D the company's fastest gaming desktop processor. The Ryzen 9 9900X3D is similarly interesting—you get a base frequency of 4.40 GHz, and 5.50 GHz maximum boost frequency, which is higher than that of the 9800X3D, although the CCD with the 3D V-Cache only has 6 cores. The 9950X3D should hence end up beating the 9800X3D in gaming workloads, while the 9900X3D should be either on par or slightly slower than the 9800X3D at gaming, although faster than any chip from the non-X3D Ryzen 9000 series.
AMD claims that the Ryzen 9 9950X3D is on average 8% faster than the 7950X3D, and on average 20% faster than the Intel Core Ultra 9 285K in gaming workloads, tested across 40 games. It's also 13% faster than the 7950X3D at productivity, and 10% faster than the 285K across the same productivity tests. The company hence claims that the 9950X3D will be the "world's best processor" for both gaming and productivity, ceding no ground to Intel. The company made no first-party performance claims for the 9900X3D. AMD says that the Ryzen 9 9950X3D and 9900X3D will be available in Q1 2025.
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63 Comments on AMD Launches Ryzen 9 9000X3D Series "Zen 5" Desktop Processors with 3D V-Cache

#26
igormp
ShakalliaIt says so in the article, its coming from the presentation :"and AMD has worked to refine its software-based OS scheduler optimization such that productivity applications favor either of the CCDs, while games stick to the one with 3D V-Cache."
It's not "disabled", other background stuff can still run in the non-x3D CCD, but games get "pinned" to the X3D CCD. Similar to how you can pin a process to some specific cores with something like process lasso.
freeagentOh..

Now load up more cores and see the clocks falling :p
Posted on Reply
#27
Shakallia
freeagentOh..

You can get that kind of result with any processor if you lucky on the silicon lottery, because it always comes to that, may you buy a 9600x, 9700x, 9900x or 9950x etc..
igormpIt's not "disabled", other background stuff can still run in the non-x3D CCD, but games get "pinned" to the X3D CCD. Similar to how you can pin a process to some specific cores with something like process lasso.

Now load up more cores and see the clocks falling :p
Yes, I was only speaking for gaming. Its disabled for gaming, that's how I meant it. If you read my first post, I was explicitly talking about gaming scenarios.

I'm quoting myself here :" In gaming, the other ccd is disabled"
Posted on Reply
#28
igormp
ShakalliaYou can get that kind of result with any processor if you lucky on the silicon lottery, because it always comes to that, may you buy a 9600x, 9700x, 9900x or 9950x etc..


Yes, I was only speaking for gaming. Its disabled for gaming, that's how I meant it. If you read my first post, I was explicitly talking about gaming scenarios.

I'm quoting myself here :" In gaming, the other ccd is disabled"
I got what you meant, it's just a semantics issue. Disabled implies it doesn't work/can't be used, which is not the case.
If a game for some reason requires more cores, even with this scheduler prioritization it could spill into the 2nd CCD given the x3D ones becomes too busy.
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#29
Guwapo77
This is going to be the best gaming chip on the planet. Same frequency as the non X3D part, its going to be magical. As soon as its available for purchase, its bought!
Posted on Reply
#30
Crackong
Disappointed to see no dual CCD dual X3D part tho.
Posted on Reply
#31
Bagerklestyne
Now more than ever I want to see a frequency locked 7800X3D and 9800X3D (say 4 to 4.5ghz) so we can see how much was generational ipc and how much simply boost clock.
Posted on Reply
#32
Shakallia
igormpI got what you meant, it's just a semantics issue. Disabled implies it doesn't work/can't be used, which is not the case.
If a game for some reason requires more cores, even with this scheduler prioritization it could spill into the 2nd CCD given the x3D ones becomes too busy.
I'm not convinced at all, especially given the fact that core parking is a way to avoid latency issue between the 2 ccd's, so I believe that by tweaking it (the scheduler), they kind of imply enforcing the fact that the games only uses the x3d ccd cores.
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#33
mkppo
Meh, i'll still get it in the hope of getting luckier than my 9950X and it's garbo IMC. Should pair up nicely with the Apex. Atleast now there's no productivity penalty compared to 9950X.
Posted on Reply
#34
bug
ShakalliaYou clearly do not understand that only ONE ccd has 3dv cache. In gaming, the other ccd is disabled, so you're basically comparing two 8 core 3dvcache processors, one with higher boost clock and lower base frequency, and one with higher base frequency abd lower boost clock.
The cores are still there. They will be used if the others are under load. The 3DVCache cores will be preferred, that's all.
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#35
trparky
Why AMD!? Why only one CCD with 3D cache?
Posted on Reply
#36
Aken Bosch
trparkyWhy AMD!? Why only one CCD with 3D cache?
Cost and diminishing returns (more likely). The generation that will launch along with the new consoles I'm sure they will though (call it a hunch).
Posted on Reply
#37
trparky
Aken BoschCost and diminishing returns (more likely). The generation that will launch along with the new consoles I'm sure they will though (call it a hunch).
But why not have an option to buy dual 3D cache models?
Posted on Reply
#38
Aken Bosch
Desktop CPU's. You'll get dangerously close to server territory, where the margins are higher. Why would you kill a gold goose?
Posted on Reply
#39
bug
trparkyWhy AMD!? Why only one CCD with 3D cache?
The answer is right there: Core Complex Die. You cannot have on-die cache across two dies. You could have two different caches, but they will not help much, since the data wouldn't be coherent.
Posted on Reply
#40
trparky
bugThe answer is right there: Core Complex Die. You cannot have on-die cache across two dies. You could have two different caches, but they will not help much, since the data wouldn't be coherent.
But the L3 cache on non-3D cache chips aren't coherent either. What's the difference between a CCD with 3D cache and one without? Not much from what I can see other than that 3D cache gives a whole lot more L3 cache.
Posted on Reply
#41
bug
trparkyBut the L3 cache on non-3D cache chips aren't coherent either. What's the difference between a CCD with 3D cache and one without? Not much from what I can see other than that 3D cache gives a whole lot more L3 cache.
Bingo!
Posted on Reply
#42
trparky
So why not have two CCDs as versus one CCD that have shit loads of L3 cache?
Posted on Reply
#43
bug
trparkySo why not have two CCDs as versus one CCD that have shit loads of L3 cache?
That's chiplet design for you. Chiplets are only as big as you can make without too many defects.
Posted on Reply
#44
trparky
bugThat's chiplet design for you. Chiplets are only as big as you can make without too many defects.
But correct me if I'm wrong but don't all CCDs, even the 3D cache CCDs, start off as plain CCDs and the 3D cache is just bolted to it?
Posted on Reply
#45
bug
trparkyBut correct me if I'm wrong but don't all CCDs, even the 3D cache CCDs, start off as plain CCDs and the 3D cache is just bolted to it?
I couldn't tell how they're made otoh. But even if they were made the way you describe, you have yields for the CCD, yields for the cache and then yields for the finished product (because simply combining them together can break some).

Regardless, even if both CCDs would have 3DCache added, migrating threads would need their data pulled again from RAM which I suspect negates the advantage of 3DVCache. Probably the numbers (which only AMD has) indicated you win more benchmarks if you put a bigger cache on one CCD than if you put a smaller cache on both CCDs.
Posted on Reply
#46
trparky
bugI couldn't tell how they're made otoh. But even if they were made the way you describe, you have yields for the CCD, yields for the cache and then yields for the finished product (because simply combining them together can break some).
I didn't think about that.
bugRegardless, even if both CCDs would have 3DCache added, migrating threads would need their data pulled again from RAM which I suspect negates the advantage of 3DVCache.
Another thing I didn't think about. Yeah, that makes sense.

I guess I was just caught up in the idea of more cache, more better.
Posted on Reply
#47
bug
trparkyI guess I was just caught up in the idea of more cache, more better.
There's this knee-jerk reaction that you see on the Internet, that companies have their engineers neuter their products for various reason (depending on what you read, someone will have that opinion about any company). That leaves an impression and can add some thought-bias. And while I am sure in some cases that is true, what usually happens is engineers will come up with something on the drawing board and that something gets adjusted because a) real world testing and b) production/supply realities.

In particular "the more cache, the better" was never true. Because the more cache, the higher the latency. Correctly sizing a cache for an architecture is so complicated that, as you can see, landed us with 4 levels of cache, each still able to put more performance on the table. Without the latency problem, we'd have one huge 1st level cache (kidding, that's not possible, for different reasons).
Posted on Reply
#48
igormp
bugI couldn't tell how they're made otoh. But even if they were made the way you describe, you have yields for the CCD, yields for the cache and then yields for the finished product (because simply combining them together can break some).
AFAIK the V-cache is made on a cheaper node (expected since it's both cheaper and SRAM has shitty size scaling anyway).
Posted on Reply
#49
trparky
bugBecause the more cache, the higher the latency.
Why is that?
Posted on Reply
#50
bug
trparkyWhy is that?
Eh...
For a naive answer, look here (look past the first couple of paragraphs, they're not a good explanation): electronics.stackexchange.com/a/82883
For a less naive answer, look at the link at the end of the response.
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