Wednesday, March 26th 2025
Sarcina Technology Launches AI Chiplet Platform Enabling Systems Up to 100x100 mm in a Single Package
Sarcina Technology, a global semiconductor packaging specialist, is excited to announce the launch of its innovative AI platform to enable advanced AI packaging solutions that can be tailored to meet specific customer requirements. Leveraging ASE's FOCoS-CL (Fan-Out Chip-on-Substrate-Chip Last) assembly technology, this platform includes an interposer which supports chiplets using UCIe-A for die-to-die interconnects, allowing for the delivery of cost-effective, customizable, cutting-edge solutions.
Sarcina Technology is on a mission to push the boundaries of AI computing system development by providing a unique platform that enables efficient, scalable, configurable and cost-effective semiconductor packaging solutions for AI applications. As AI workloads continue to evolve, there is a need for increasingly sophisticated packaging solutions capable of supporting higher computational demands. Sarcina's novel interposer packaging technology integrates leading memory solutions with high-efficiency interconnects. Whether prioritizing cost, performance or power-efficiency, Sarcina's new AI platform can deliver.
According to Dr. Larry Zu, CEO of Sarcina Technology:
Sarcina has extensive expertise in designing high-power, high-performance semiconductor packages. This allows semiconductor startups to focus on developing efficient algorithms for generative AI and edge AI training without the need for an expensive post-silicon design and manufacturing team. Startups can simply develop their silicon and pass it to Sarcina for post-silicon packaging, streamlining the process and reducing costs while maintaining high performance. Sarcina's die-to-die interposer solution enables AI customers to use chiplets to form large silicon areas, supporting high-performance computing with satisfactory wafer yields. This large package design allows for the integration of more memory, which is crucial for generative AI applications that require rapid, parallel data processing.
Key features of the new Sarcina AI platform:
Source:
Sarcina Technology
Sarcina Technology is on a mission to push the boundaries of AI computing system development by providing a unique platform that enables efficient, scalable, configurable and cost-effective semiconductor packaging solutions for AI applications. As AI workloads continue to evolve, there is a need for increasingly sophisticated packaging solutions capable of supporting higher computational demands. Sarcina's novel interposer packaging technology integrates leading memory solutions with high-efficiency interconnects. Whether prioritizing cost, performance or power-efficiency, Sarcina's new AI platform can deliver.
"Six years ago, after prototyping a 2.5D silicon TSV interposer package that integrated one ASIC and two HBMs, we predicted this technology would enable highly complex compute solutions. Today, this vision is becoming a reality, driven by RDL die-to-die interconnects like UCIe."The Sarcina team has successfully developed an interposer with up to 64 bits of data interface per module, achieving data rates of up to 32 GT/s. This delivers the highest UCIe-A performance in terms of both bandwidth and data rate, as specified by the UCIe 2.0 standard. To further enhance data transfer throughput, multiple modules can be arranged in parallel along the silicon die edge. There is also a choice between LPDDR5X/6 packaged memory chips and HBMs.
Zu continues: "With FOCoS assembly technology, we are entering a new era of AI computing. Our AI platform offers greater efficiency and customization, with the lowest cost in the industry for generative AI chips. This ensures that our customers stay competitive in the rapidly evolving AI landscape."
Sarcina has extensive expertise in designing high-power, high-performance semiconductor packages. This allows semiconductor startups to focus on developing efficient algorithms for generative AI and edge AI training without the need for an expensive post-silicon design and manufacturing team. Startups can simply develop their silicon and pass it to Sarcina for post-silicon packaging, streamlining the process and reducing costs while maintaining high performance. Sarcina's die-to-die interposer solution enables AI customers to use chiplets to form large silicon areas, supporting high-performance computing with satisfactory wafer yields. This large package design allows for the integration of more memory, which is crucial for generative AI applications that require rapid, parallel data processing.
Key features of the new Sarcina AI platform:
- Cost-effective chiplet design: A cost-efficient alternative to expensive SoC solutions.
- Fast die-to-die interconnection with UCIe-A standard: Up to 64-bit data interface per module and 32 GT/s transmission speed per lane. Supports multi-module configurations, interconnect redundancy and sideband configurations as specified by UCIe 2.0 standards.
- FOCoS-CL advanced packaging technology: A cost-effective replacement for costly 2.5D TSV (Through-Silicon Via) silicon interposer technology, as well as other expensive solutions like silicon bridge die with fan-out RDL interconnections.
- LPDDR5X/6 and HBM options: Provides superior memory bandwidth and efficiency to support a variety of AI workloads. LPDDR6 memory also incorporates 3D stacking technology similar to HBM, achieving data rates of approximately 10 GT/s.
- Scalable package size: Supports package sizes up to 100 mm x 100 mm, enabling scalability for diverse AI applications.
- Power specifications: <500 W for forced air cooling and up to 1000 W with liquid cooling, offering flexible deployment options.
- Memory integration: Supports up to 20 LPDDR5X/6 memory chips or up to 8 HBM3E chips, facilitating high-speed data processing for AI workloads.
2 Comments on Sarcina Technology Launches AI Chiplet Platform Enabling Systems Up to 100x100 mm in a Single Package
Figure up to 12x~50mm chiplets, ~200mm2 IC, plus whatever the main Media and I/O die is (~100mm2?) plus bridge chips or whatever. That adds up to ~1000mm2 on an interposer real quick.
At high clocks on N3P or N3X something like that could very well be close to 1000w.
If such design existed. That's why I wonder if they'll go above 3/4 that (especially on N3E). Especially when we know it'll probably operate at 1.1-1.2v (for IC, not unlike v-cache/HBM), not more silicon at low voltage.
TLDR: I expect first-gen UDNA to be a lot like 5800x3D (with first-gen v-cache), with very similar design limitations.
Any way you look at it, I don't think any optimized 512-bit design (meaning using the full potential of even the densest version of the process) are feasible within ~675w on 3nm.
You could underclock it, sure, and probably at threshold voltage use half the power (say around 500w or so), but that's unarguably wasting it's potential versus using a more simple design and higher clocks.
It's very possible a company like nVIDIA may do something like that just to get the pure performance win within that power envelop, but it's a waste IMHO.
That's why both 500w (air) and 1000w (water) are described in this scenario; threshold and maximum voltage.
Figure a ~900w design, minus 200w of ram, 700w general chip(s) operating @ 1.2v, where-as at ~.7v it would be ~300w + 200w.
Again, just a theoretical example to understand why the variably and possibility.
I don't know exact designs any company will go with beyond figuring out some things just aren't feasible (in most cases and IMHO) for exactly that reason.