Intel "Rocket Lake-S" Die Annotated
Intel is betting big on an 8-core processor to revive its gaming performance leadership, and that chip is the 11th Generation Core "Rocket Lake-S," coming this March. In its 2021 International CES online event, Intel disclosed more details about "Rocket Lake-S," including the first true-color die-shot. PC enthusiast @Locuza_ on Twitter annotated the die for your viewing pressure. For starters, nearly half the die-area of the "Rocket Lake-S" is taken up by the uncore and iGPU, with the rest going to the eight "Cypress Cove" CPU cores.
The "Cypress Cove" CPU core is reportedly a back-port of "Willow Cove" to the 14 nm silicon fabrication node, although there are some changes, beginning with its cache hierarchy. A "Cypress Cove" core is configured with the same L1I and L1D cache sizes as "Willow Cove," but differ with L2 and L3 cache sizes. Each "Cypress Cove" core is endowed with 512 KB of dedicated L2 cache (which is a 100% increase from the 256 KB on "Skylake" cores); but this pales in comparison to the 1.25 MB L2 caches of "Willow Cove" cores on the "Tiger Lake-U" silicon. Also, the L3 cache for the 8-core "Rocket Lake-S" die is 16 MB, spread across eight 2 MB slices; while the 4-core "Tiger Lake-U" features 12 MB of L3, spread across four 3 MB slices. Each core can address the whole L3 cache, across all slices.
The "Cypress Cove" CPU core is reportedly a back-port of "Willow Cove" to the 14 nm silicon fabrication node, although there are some changes, beginning with its cache hierarchy. A "Cypress Cove" core is configured with the same L1I and L1D cache sizes as "Willow Cove," but differ with L2 and L3 cache sizes. Each "Cypress Cove" core is endowed with 512 KB of dedicated L2 cache (which is a 100% increase from the 256 KB on "Skylake" cores); but this pales in comparison to the 1.25 MB L2 caches of "Willow Cove" cores on the "Tiger Lake-U" silicon. Also, the L3 cache for the 8-core "Rocket Lake-S" die is 16 MB, spread across eight 2 MB slices; while the 4-core "Tiger Lake-U" features 12 MB of L3, spread across four 3 MB slices. Each core can address the whole L3 cache, across all slices.