Monday, November 12th 2018
AMD "Zen 2" IPC 29 Percent Higher than "Zen"
AMD reportedly put out its IPC (instructions per clock) performance guidance for its upcoming "Zen 2" micro-architecture in a version of its Next Horizon investor meeting, and the numbers are staggering. The next-generation CPU architecture provides a massive 29 percent IPC uplift over the original "Zen" architecture. While not developed for the enterprise segment, the stopgap "Zen+" architecture brought about 3-5 percent IPC uplifts over "Zen" on the backs of faster on-die caches and improved Precision Boost algorithms. "Zen 2" is being developed for the 7 nm silicon fabrication process, and on the "Rome" MCM, is part of the 8-core chiplets that aren't subdivided into CCX (8 cores per CCX).
According to Expreview, AMD conducted DKERN + RSA test for integer and floating point units, to arrive at a performance index of 4.53, compared to 3.5 of first-generation Zen, which is a 29.4 percent IPC uplift (loosely interchangeable with single-core performance). "Zen 2" goes a step beyond "Zen+," with its designers turning their attention to critical components that contribute significantly toward IPC - the core's front-end, and the number-crunching machinery, FPU. The front-end of "Zen" and "Zen+" cores are believed to be refinements of previous-generation architectures such as "Excavator." Zen 2 gets a brand-new front-end that's better optimized to distribute and collect workloads between the various on-die components of the core. The number-crunching machinery gets bolstered by 256-bit FPUs, and generally wider execution pipelines and windows. These come together yielding the IPC uplift. "Zen 2" will get its first commercial outing with AMD's 2nd generation EPYC "Rome" 64-core enterprise processors.
Update Nov 14: AMD has issued the following statement regarding these claims.
Source:
Expreview
According to Expreview, AMD conducted DKERN + RSA test for integer and floating point units, to arrive at a performance index of 4.53, compared to 3.5 of first-generation Zen, which is a 29.4 percent IPC uplift (loosely interchangeable with single-core performance). "Zen 2" goes a step beyond "Zen+," with its designers turning their attention to critical components that contribute significantly toward IPC - the core's front-end, and the number-crunching machinery, FPU. The front-end of "Zen" and "Zen+" cores are believed to be refinements of previous-generation architectures such as "Excavator." Zen 2 gets a brand-new front-end that's better optimized to distribute and collect workloads between the various on-die components of the core. The number-crunching machinery gets bolstered by 256-bit FPUs, and generally wider execution pipelines and windows. These come together yielding the IPC uplift. "Zen 2" will get its first commercial outing with AMD's 2nd generation EPYC "Rome" 64-core enterprise processors.
As we demonstrated at our Next Horizon event last week, our next-generation AMD EPYC server processor based on the new 'Zen 2' core delivers significant performance improvements as a result of both architectural advances and 7nm process technology. Some news media interpreted a 'Zen 2' comment in the press release footnotes to be a specific IPC uplift claim. The data in the footnote represented the performance improvement in a microbenchmark for a specific financial services workload which benefits from both integer and floating point performance improvements and is not intended to quantify the IPC increase a user should expect to see across a wide range of applications. We will provide additional details on 'Zen 2' IPC improvements, and more importantly how the combination of our next-generation architecture and advanced 7nm process technology deliver more performance per socket, when the products launch.
162 Comments on AMD "Zen 2" IPC 29 Percent Higher than "Zen"
For the rest of it, what exact tests are those? Zen2 apparently gets proper AVX which will indeed boost certain workloads considerably.
Lisa Su is very careful about the guidance she puts out.
Edit:
I was wrong, AMD does say these tests measure IPC.
ir.amd.com/news-releases/news-release-details/amd-takes-high-performance-datacenter-computing-next-horizonDidn't Zen have hardware acceleration for RSA?
If Zen1 IPC is 1.00
Zen2 IPC is 29% higher than Zen1, so it will be 1.29
This means, that:
Zen1 will handle 1 instruction per 1 clock cycle
Zen2 will handle 1.29 instructions per 1 clock cycle.
If you your task requires 1000 instructions to be completed, then:
Zen1 will finish this task in 1000 clock cycles;
Zen2 will finish this task in 775 clock cycles.
That would be waking up to a new reality, one that existed last time over 12 years ago. Point some guns at me, i have skepticism about that.
Is this confirmed, that the CCXs are 8 cores now? I don't think i've seen it explicited anywhere, would there be a source?
The chiplets themselves are quite small, and 2 of them could very possibly fit into a dual-chiplet AM4 CPU with 16 cores.
If ill have to bet, im taking a guess that they will always appear in full physical form, and of course AMD is going to take a freedom of shutting down cores, letting us also enjoy 10-12 core parts on AM4.
With Zen gen 1 they were huge compered to those.
Personally my concern is with latency but, I'm not sure if that's an unfounded issue or not. It's likely the case that it's more beneficial to move the I/O components. It's also possible that the I/O hub might not need to be done on the same process as the CCXs which might further improve yields if the larger die is being done on a more mature process.
I'm interested to see how Rome turns out because if it turns out well, it means that AMD is keeping up the pace that started with the first Zen chips which is necessary to keep Intel on the offensive. If AMD can effectively double the number of cores without too much more cost, then Intel is going to remain on the defensive.
Intel: We can make mainstream 8c/16t CPUs too.
AMD: Hold my beer.
My guess is that it could be from GF which keeps GF in the game.
@TheGuruStud I would think they will make all the chiplets 8c, but should still be able to cut them down for market segmentation and using ones with faulty parts. I'm sure that's what @bubbleawsome meant, buying a 6-core CPU that could be 1 x 8 core with 2 faulty cores or, if space allows on the AM4 package, potentially 2 x 8 cores with 10 faulty cores between them (the latter being less likely, those would more likely go to TR or Epyc parts depending on the clock speeds but it could be done).
Even the price is not that out of this world, but at $500 it won't gain 10% market share, so yeah, not that mainstream after all.