Tuesday, January 29th 2019
SK Hynix Fellow Says PC5 DDR5 by 2020, DDR6 Development Underway
The PC5 DDR5 main memory standard could enter the market by 2020, according to SK Hynix research fellow Kim Dong-Kyun. The first such memory standard will be DDR5-5200, which offers nearly double the bandwidth of DDR4-2666. "We are discussing several concepts of the post DDR5," he said. "One concept is to maintain the current trend of speeding up the data transmission, and another is to combine the DRAM technology with system-on-chip process technologies, such as CPU," he added, without offering any additional information. SK Hynix had in 2018 developed a working prototype of a 16-gigabit (2 GB) DDR5 DRAM chip ticking at 5200 MT/s, at 1.1 Volts. A 64-bit wide memory module made with these chips could offer bandwidth of 41.6 GB/s.
SK Hynix is developing its own innovations that could make its DDR5 chips more advanced than the competition without going off-standard. "We have developed a multi-phase synchronization technology that enables keeping the voltage during a high-speed operation in a chip at a low level by placing multiple phases within the IP circuit, so the power used on each phase is low but the speed is high when combined," Kim said. He also mentioned that development of the DDR6 PC memory standard is already underway, with the design goals of doubling bandwidth and densities over DDR5. Advancements in DRAM are propelled not just by the PC ecosystem, but also handhelds and self-driving car electronics.
Source:
CDRInfo
SK Hynix is developing its own innovations that could make its DDR5 chips more advanced than the competition without going off-standard. "We have developed a multi-phase synchronization technology that enables keeping the voltage during a high-speed operation in a chip at a low level by placing multiple phases within the IP circuit, so the power used on each phase is low but the speed is high when combined," Kim said. He also mentioned that development of the DDR6 PC memory standard is already underway, with the design goals of doubling bandwidth and densities over DDR5. Advancements in DRAM are propelled not just by the PC ecosystem, but also handhelds and self-driving car electronics.
11 Comments on SK Hynix Fellow Says PC5 DDR5 by 2020, DDR6 Development Underway
Oh, also I heard somewhere that DDR5 also has some 'per clock' enhancements (more data per transfer) over DDR4 so it would provide even more bandwidth than 41GB/s I think for that 64bit channel at 5.2gt/s or is that transfer rate effective with the enhancements already?
With CAS Latency of 20, 8 clocks burst, 2 clocks for cpu to ram to cpu, every 30 clocks DDR5 can transfer 8 clocks of data or 11 GB/s real,
Nah my rig is absolutely too ancient, Xeon1240v1 to the rescue. Sandy bridge 10 years.
Hynix: Heres why