Scaling and manufacturing of ever shrinking semiconductor devices is becoming more challenging as smaller nodes are introduced. As we have approached 7 nanometers, economies of scale are becoming more influential than scales of manufacturing. For example, the development of the 7 nm node development cost more than 3 billion USD, while smaller nodes are expected to see that price cross the 5 billion USD mark. So given that we are approaching the limit where we can't squeeze more transistors in two-dimensional space without huge economical impact, we have to utilize another dimension in order to keep performance improvements coming.

AMD has filed a patent for cooling a 3D stacked memory with thermo-electric coolers - TECs, also known as Peltier devices. Being that TECs are made out of P-type and N-type semiconductors, they can easily be integrated into existing silicon manufacturing methods and controlled like a regular device. The process AMD has patented basically describes how to insert the TEC between memory and logic devices, where it draws heat from either logic or memory with each side being able to dissipate the heat. That effect is possible due to nature of TEC, where the direction of heat flow is changed inverting the voltage.As you can see, this is the high-level overview of what AMD proposes, with constant measurements of both the logic stack and memory stack, to determine which one is hotter. The hotter side gets heat drawn away from it to the colder side, which can dissipate that heat.

This solution would be useful in devices that are similar to Intel's Foveros, where you have a memory die on top of logic:However, thermoelectric cooling is not free - it does consume power, and generates some heat on its own, so we'll have to wait and see whether this can actually turn into a useful technology.

You can read the whole patent here.