Tuesday, August 6th 2019

Next-generation Intel Xeon Scalable Processors to Deliver Breakthrough Platform Performance with up to 56 Processor Cores

Intel today announced its future Intel Xeon Scalable processor family (codename Cooper Lake) will offer customers up to 56 processor cores per socket and built-in AI training acceleration in a standard, socketed CPU as part of its mainline Intel Xeon Scalable platforms, with availability in the first half of 2020. The breakthrough platform performance delivered within the high-core-count Cooper Lake processors will leverage the capabilities built into the Intel Xeon Platinum 9200 series, which today is gaining momentum among the world's most demanding HPC customers, including HLRN, Advania, 4Paradigm, and others.

"The Intel Xeon Platinum 9200 series that we introduced as part of our 2nd Generation Intel Xeon Scalable processor family generated a lot of excitement among our customers who are deploying the technology to run their high-performance computing (HPC), advanced analytics, artificial intelligence and high-density infrastructure. Extended 56-core processor offerings into our mainline Intel Xeon Scalable platforms enables us to serve a much broader range of customers who hunger for more processor performance and memory bandwidth."
-Lisa Spelman, vice president and general manager of Data Center Marketing, Intel Corporation
The future Intel Xeon Scalable processors (codename Cooper Lake) will deliver twice the processor core count (up to 56 cores), higher memory bandwidth, and higher AI inference and training performance compared to the standard Intel Xeon Platinum 8200 processor. The future 56-core Cooper Lake processor is expected to deliver a lower power envelope than the current Intel Xeon Platinum 9200 processors. Cooper Lake will be the first x86 processor to deliver built-in high-performance AI training acceleration capabilities through new bfloat16 support added to Intel Deep Learning Boost (Intel DL Boost ). Cooper Lake will have platform compatibility with the upcoming 10nm Ice Lake processor.

For more than 20 years, Intel Xeon processors have delivered the platform and performance leadership that gives data center and enterprise customers the flexibility to pick the right solution for their computing needs. Next-generation Intel Xeon Scalable processors (Cooper Lake) build off Intel's uninterrupted server processor track record by delivering leadership performance for customers' real-world workloads and business application needs.

Intel Xeon Platinum 9200 processors are available for purchase today as part of a pre-configured systems from select OEMs, including Atos, HPE, Lenovo, Penguin Computing, Megware and authorized Intel resellers. Learn more information about the Intel Xeon Platinum 9200 processors.
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56 Comments on Next-generation Intel Xeon Scalable Processors to Deliver Breakthrough Platform Performance with up to 56 Processor Cores

#51
londiste
Berfs1Yall acting like you know everything, tell my why this particular CPU says it supports 128 lanes? www.amd.com/en/products/cpu/amd-epyc-7551p
Don't even tell me "dual socket", its a P CPU. Clearly my glasses are working.
Yes, single-socket EPYC has 128 lanes.
Context of my comment was dual socket. It is not as simple as dual socket having 2x128 lanes. Dual socket Naples has 128 lanes. Dual socket Rome can have more - 128 is the default but OEM can configure it to be 160-192 lanes.
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#52
Patriot
Ffs no one ever said 1 cpu didn't have 128 pcie lanes... Just that a 2p system doesn't have 256... Now go back and read as to why that is so rather than shouting off Mt stupid.
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#53
Berfs1
PatriotFfs no one ever said 1 cpu didn't have 128 pcie lanes... Just that a 2p system doesn't have 256... Now go back and read as to why that is so rather than shouting off Mt stupid.
A 2P system has 256 PCIe lanes from the CPUs. I never said 256 usable PCIe lanes.
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#54
jaggerwild
And not one person that posted will ever even see this CPU, SMMH! OK back to why AMD CPU'S wont over clock...................:clap:
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#55
Patriot
Berfs1A 2P system has 256 PCIe lanes from the CPUs. I never said 256 usable PCIe lanes.
No, you clearly did not understand the architecture one bit by your earlier posts which have already been quoted so don't bother trying to change them, here, I will quote again for you.
Berfs1No, it is 128 PER CPU. AMD confirms it on their website. You have a total of 256 with 2 Epyc CPUs. Though, finding a way to USE all 256, that’ll require lots of hardware (but I’m sure some server users will find a way to use that many). Plus for second gen, its 128 PCIe 4.0 lanes per cpu. That’s yummy.
See, you thought you could use all 256 lanes and you were quite emphatic about 1+1 =2 for a very annoyingly long time, and instead of reading the replies on how there were no dedicated interconnects and how it was a amazingly scalable programmable fabric... where half the lanes of naples point at each other in 4 xgmi links and with the doubling of bandwidth in rome they enable you to use 1 xgmi link for 32 more lanes. (one person said 2 but I have not seen that in the wild nor think it's a good idea.) so 128 for 2p with 4 xgmi links and 160 for 2p with 3 xgmi links.

You had correct information that 1 cpu has 128 lanes, and no one disagreed with it. But you kept pointing at it when people told you that 2x didn't have 256 usable. but I am glad we are on the same page now.
jaggerwildAnd not one person that posted will ever even see this CPU, SMMH! OK back to why AMD CPU'S wont over clock...................:clap:
I actually have a 7601 that I am playing with and I will get rome, though probably not the 64c as I don't need that many threads, I need clocks.
Fun fact, all Epyc's are unlocked. :) ...Though the msr's for Rome have not been discovered yet nor has an updated BKDG. (bios kernel dev guide)
Also unfun note... many gen 1 epyc boards don't support rome due to same fucking cheap issue as desktop. Too small of soldered rom chip.
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