Thursday, May 14th 2020
NVIDIA "Ampere" Designed for both HPC and GeForce/Quadro
NVIDIA CEO Jensen Huang in a pre-GTC press briefing stressed that the upcoming "Ampere" graphics architecture will spread across both the company's compute-accelerator and commercial graphics product lines. The architecture makes its debut later today with the Tesla A100 HPC processor for breakthrough AI acceleration. It's unlikely that any GeForce products will be formally announced this month, with rumors pointing to a GeForce "Ampere" product launch at a gaming-focused event in September, close to "Cyberpunk 2077" launch.
It was earlier believed that NVIDIA had forked its breadwinning IP into two lines, one focused on headless scalar compute, and the other on graphics products through the company's GeForce and Quadro product lines. To that effect, its "Volta" architecture focused on scalar-compute (with the exception of the forgotten TITAN V); and the "Turing" architecture focused solely on GeForce and Quadro. It was then believed that "Ampere" will focus on compute, and the so-called "Hopper" would be this generation's graphics-focused architecture. We now know that won't be the case. We've compiled a selection of GeForce Ampere rumors in this article.
Source:
MarketWatch
It was earlier believed that NVIDIA had forked its breadwinning IP into two lines, one focused on headless scalar compute, and the other on graphics products through the company's GeForce and Quadro product lines. To that effect, its "Volta" architecture focused on scalar-compute (with the exception of the forgotten TITAN V); and the "Turing" architecture focused solely on GeForce and Quadro. It was then believed that "Ampere" will focus on compute, and the so-called "Hopper" would be this generation's graphics-focused architecture. We now know that won't be the case. We've compiled a selection of GeForce Ampere rumors in this article.
17 Comments on NVIDIA "Ampere" Designed for both HPC and GeForce/Quadro
And the apparent 7nm die size limitation has already been put to bed.
AMD has built four dies - chiplet 74 sq. mm, Navi 10 251 sq. mm, Vega 20 that is 331 sq. mm and Renoir that is 156 sq. mm (62.82 MTr/sq. mm).
It is quite possible that the first iteration of the N7 process, namely the TSMC N7FF has indeed a limitation up to 429 sq. mm.
Otherwise, why is Nvidia is late if not to wait the next processes ?65.37 MTr/ sq. mm if 54B and 826.
What cost do you mean - the one that is always transfered to the buyers? How much does the RX 5700 cost and does AMD have competition to Nvidia's RTX 2080, RTX 2080 S, RTX 2080 Ti, RTX Titan and Volta ? No!
Lo and behold, a couple of years later Turing was still about big, expensive dies. And that was the first time Nvidia did that (that I can recall), they have never hinted at splitting their architectures. In fact, if you look at their MO, they're optimizing costs by unifying everything that makes sense to be unified.
"AMD had never built so small dies on average" Cmon now, remember your history lessons. AMD's entire marketing push for the HD 3000/4000/5000/6000 series was "small efficient dies".
And also, that was after the R600 disaster and they were scared to build larger dies, Fiji is 596 sq. mm!
You stated that AMD had never built a line of small dies, I showed you that was factually incorrect. AMD has done this higher density smaller die strategy before, this is nothing new.
It has to do that AMD had never abandoned the enthusiasts segment before the N7 process.