Friday, October 29th 2021
Intel "Alder Lake-S" Comes in a 6+0 Core Die Variant
Intel's 12th Gen Core "Alder Lake-S" silicon apparently comes in two variants based on core count. The first one is a larger variant with 8 P cores and 8 E cores, while the second variant is a visibly smaller die with only 6 P cores, no E cores. This was revealed by an MSI Insider video presentation where pictures of LGA1700 packages with the two die types were shown off.
MSI also confirmed die-sizes and dimensions of the two. The larger C0 die measures 10.5 mm x 20.5 mm, working out to 215.25 mm² area. The smaller H0 die measures 10.5 mm x 15.5 mm, and a die area of 162.75 mm². The H0 silicon completely lacks "Gracemont" E-core clusters, and physically features six "Golden Cove" P cores. It's possible that given the 3 MB L3 slice size on the larger C0 silicon, the smaller H0 silicon physically features 18 MB of shared L3 cache.
Apparently the 12th Gen Core i5 series will have two classes of SKUs. One based on the C0 silicon, with 6+4 (P+E) configuration, and the other based on the H0 silicon, with 6+0 core configuration. The already launched Core i5-12600K/KF are 6+4 core, and it's expected that the i5-12600 (non-K) will have the same core-count, too. The lower Core i5 SKUs, such as the i5-12400 and i5-12400F, could be 6+0 core. Intel probably adopted this segmentation within the Core i5 lineup to ensure that the $170-$190 SKUs, such as the i5-12400/F don't cannibalize sales of the i5-12600/K/KF/F. The company had been carrying out similar segmentation within the Core i3 series in the past few generations, where the i3-xx100 and i3-xx300 series SKUs are differentiated with L3 cache sizes.
We recently spotted an i5-12400 engineering sample that confirms this core-configuration. The decision to create a smaller die for desktop could be purely economics-driven. The lower end of the Core i5 series, the Core i3 series, Pentium, and Celeron, sell in high volumes, and it makes sense for Intel to use physically smaller dies to maximize wafer utilization on its latest Intel 7 node (10 nm Enhanced SuperFin). It's also possible that the 12th Gen Core i3 series will be carved out from this silicon, by disabling two of the six P cores.
Source:
MSI Insider (YouTube)
MSI also confirmed die-sizes and dimensions of the two. The larger C0 die measures 10.5 mm x 20.5 mm, working out to 215.25 mm² area. The smaller H0 die measures 10.5 mm x 15.5 mm, and a die area of 162.75 mm². The H0 silicon completely lacks "Gracemont" E-core clusters, and physically features six "Golden Cove" P cores. It's possible that given the 3 MB L3 slice size on the larger C0 silicon, the smaller H0 silicon physically features 18 MB of shared L3 cache.
64 Comments on Intel "Alder Lake-S" Comes in a 6+0 Core Die Variant
That's a great way to reap the benefits of Golden Cove without being forced to bet everything on Microsoft and Thread Director doing their jobs properly. I can't help but wonder if you can just disable E-cores altogether on all of these chips though, especially for benching and whatnot.
Now I am more interested then ever in a Gracemont only Atom SKU with Xe graphics for budget laptops.
Also, size is very relative when it comes to these things.
www.hardwaretimes.com/intel-alder-lake-s-cpus-will-allow-disabling-of-low-power-or-high-performance-cores/
Honestly I think the importance of single thread is for some reason being deprecated, perhaps wrongly. Moar cores is fun and all but, to this day when I look at my CPU usage during something that I think runs a little slow, 99% of the time it is just using 1-4 threads and one of the cores is at 100%. I never really see all cores get busy unless I'm compressing / uncompressing something really big.
This is the one thing I noticed with the 10850K vs 10400 as far as more cores, is that patches and updates from Steam get installed faster and with less noticeable impact. Outside of that most things are limited to 1-4 threads.
Nov 4th can't come sooner and put these assumptions to rest.
Yields are fine.
I guess Intel are playing it safe this generation with the desktop silicon but I'd like to see a willingness to drop a few more P-cores to trade 4:1 for E-cores. I think most consumer stuff is either lightly-threaded or is an encode/render/transcode/compile task that will just take as many cores as it can possibly get.
For the same die-area as 8 P-cores and 8 E-cores, we could have had 4 P-cores and 24 E-cores. If an application demands more than 4C/8T of max-boost, max-IPC P-core performance then it'll probably react well to being given 24 more cores.
Ngl kinda frustrated the E-cores play the same role on desktop (ie. relied on for 90% of work until something "deserving" of P-core). Since 8th gen there's a huge discrepancy on Intel on MT perf between PL2 and PL1. The E-cores' should help bridge that perf gap - but they should be only a performance reserve, instead of this insane E-cores-all-the-time BS. It's the opposite of AMD - on the slightest twitch or click of the mouse Zen 3 will aggressively turbo for a responsive experience. And Intel also did the same, up until it suddenly decided we should pay P-core money for E-core usage :confused:
Even 14nm Intel had idle power better than chiplet Ryzen (not APU), so chasing idle/low load power on desktop is a solution searching for a problem - it's the free MT perf that Intel's looking for with the E-cores. Mobile power obviously it's always important, but frankly, for a 12400F-class desktop chip, it's irrelevant. So, 6+0 is great.