Monday, April 11th 2022

Intel Planning a Return to HEDT with "Alder Lake-X"?

Enthused with its IPC leadership, Intel is possibly planning a return to the high-end desktop (HEDT) market segment, with the "Alder Lake-X" line of processors, according to a Tom's Hardware report citing a curious-looking addition to an AIDA64 beta change-log. The exact nature of "Alder Lake-X" (ADL-X) still remains a mystery—one theory holds that ADL-X could be a consumer variant of the "Sapphire Rapids" microarchitecture, much like how the 10th Gen Core "Cascade Lake-X" was to "Cascade Lake," a server processor microarchitecture. Given that Intel is calling it "Alder Lake-X" and not "Sapphire Rapids-X," it could even be a whole new client-specific silicon. What's the difference between the two? It's all in the cores.

While both "Alder Lake" and "Sapphire Rapids" come with "Golden Cove" performance cores (P-cores), they use variants of it. Alder Lake has the client-specific variant with 1.25 MB L2 cache, a lighter client-relevant ISA, and other optimizations that enable it to run at higher clock speeds. Sapphire Rapids, on the other hand, will use a server-specific variant of "Golden Cove" that's optimized for the Mesh interconnect, has 2 MB of L2 cache, a server/HPC-relevant ISA, and a propensity to run at lower clock speeds, to support the silicon's overall TDP and high CPU core-count.
Intel probably learned from "Skylake-X" and "Cascade Lake-X" that an HEDT processor should match or exceed the mainstream-desktop part at everything (including gaming), so its buyers don't feel like performance of IPC-sensitive/less-parallelized workloads is being traded in for brute multi-threaded performance. ADL-X could hence even be a whole new silicon+package combination, with "Golden Cove" client cores, perhaps some "Gracemont" E-core clusters, and characteristic-HEDT features, such as more memory channels and more PCIe lanes; but most importantly, the ability for the processor to run some of its P-cores at very high clock-speeds.
Source: Tom's Hardware
Add your own comment

57 Comments on Intel Planning a Return to HEDT with "Alder Lake-X"?

#51
efikkan
lexluthermiesterThis. Very easily. And yet they didn't. Likewise, Intel could have easily done an expanded version of Socket 2066. And yet they didn't.

Irritating..
Yes, and I would have happily paid $50+ extra for the CPU and $100+ for the motherboard for the HEDT features.

It's a bit more complicated for Intel though…
Posted on Reply
#52
lexluthermiester
efikkanIt's a bit more complicated for Intel though…
Not really. Minimal re-engineering & retooling for the new chipsets and CPU types.
Posted on Reply
#53
Rakhmaninov3
9000 cores, 9000 TB/s, 9000 cache, 9000 pins, 9000 1000s of dollars

The Intel Yarnripper 9000
Posted on Reply
#54
efikkan
lexluthermiesterNot really. Minimal re-engineering & retooling for the new chipsets and CPU types.
The chipsets are actually a no-brainer, even the workstation chips supports the smaller CPUs with the right BIOS (as proven by those third-party motherboards from China). But getting extra PCIe lanes etc. requires some engineering, and doing even "small" die changes quickly takes >1 year to enter the market, but still doable if planned in time. So unless I misunderstood you, it's not that trivial.
Posted on Reply
#55
lexluthermiester
efikkanThe chipsets are actually a no-brainer, even the workstation chips supports the smaller CPUs with the right BIOS (as proven by those third-party motherboards from China). But getting extra PCIe lanes etc. requires some engineering, and doing even "small" die changes quickly takes >1 year to enter the market, but still doable if planned in time. So unless I misunderstood you, it's not that trivial.
PCIe lanes are almost trivial as they can load up the chipset with a bunch for extended IO and thus keeping direct-to-CPU lanes grouped in the main PCIe slots. And realistically, when they're designing a new family/revision of CPUs, they have to design the chipset along side them. So again, trivial effort IF they make the effort. They didn't. Neither did AMD. That's on both companies for failing to see the need or having the foresight to appeal to the HEDT market segment.
Posted on Reply
#56
efikkan
lexluthermiesterPCIe lanes are almost trivial as they can load up the chipset with a bunch for extended IO and thus keeping direct-to-CPU lanes grouped in the main PCIe slots.
It does not solve the problem when a CPU lacks sufficient CPU PCIe lanes.
And extra PCIe lanes through the chipset isn't sufficient for power users, as these share bandwidth. Not only can't you populate all of the PCIe, M.2, SATA ports at the same time, utilizing certain combinations of these will reduce the bandwidth left to the others.
lexluthermiesterAnd realistically, when they're designing a new family/revision of CPUs, they have to design the chipset a long side them. So again, trivial effort IF they make the effort. They didn't.
In most cases, they already are "compatible". Early development boards often are modified boards with the previous gen chipset.
Posted on Reply
#57
lexluthermiester
efikkanIt does not solve the problem when a CPU lacks sufficient CPU PCIe lanes.
True, but they would not have made an HEDT offering and skimped on the PCIe lanes, so that's not a concern.
efikkanAnd extra PCIe lanes through the chipset isn't sufficient for power users, as these share bandwidth.
While true, that doesn't mean they're useless.
Posted on Reply
Add your own comment
Dec 18th, 2024 04:45 EST change timezone

New Forum Posts

Popular Reviews

Controversial News Posts