Monday, May 16th 2022

AMD Ryzen 7000 "Phoenix" APUs with RDNA3 Graphics to Rock Large 3D V-Cache
AMD's next-generation Ryzen 7000-series "Phoenix" mobile processors are all the rage these days. Bound for 2023, these chips feature a powerful iGPU based on the RDNA3 graphics architecture, with performance allegedly rivaling that of a GeForce RTX 3060 Laptop GPU—a popular performance-segment discrete GPU. What's more, AMD is also taking a swing at Intel in the CPU core-count game, by giving "Phoenix" a large number of "Zen 4" CPU cores. The secret ingredient pushing this combo, however, is a large cache.
AMD has used large caches to good effect both on its "Zen 3" processors, such as the Ryzen 7 5800X3D, where they're called 3D Vertical Cache (3D V-cache); as well as its Radeon RX 6000 discrete GPUs, where they're called Infinity Cache. The only known difference between the two is that the latter is fully on-die, while the former is stacked on top of existing silicon IP. It's being reported now, that "Phoenix" will indeed feature a stacked 3D V-cache.The exact function of this isn't known—whether it serves as a last-level cache for the CPU or iGPU. AMD's APU architecture differs from Intel's processors that have iGPUs. On the Intel chips, the L3 cache serves as town-square for the entire SoC, with each IP block contributing an L3 cache slice that make up a functionally-contiguous cache that all IP blocks can equally address over the Ring Bus. On AMD APUs such as "Cezanne" or "Rembrandt," the L3 cache is part of the CCX (CPU cores complex), and serves exclusively as last-level cache for the CPU cores. The iGPU has its own LLC, and the Infinity Fabric interconnect is the ether binding all IP blocks on the silicon.
The obvious direction for development in future APUs could be a unification of last-level cache for the CCX and iGPU, provided the cache is large enough for the function—and this can be accomplished by stacked cache. An RDNA2 GPU with performance rivaling the RTX 3060 Laptop GPU, the Radeon RX 6650M XT, based on the "Navi 23" silicon, has 32 MB of Infinity Cache. This means, with some clever cache memory-management, an LLC size in the neighborhood of 64 MB could emerge feasible for the APU.
Source:
Greymon55 (Twitter)
AMD has used large caches to good effect both on its "Zen 3" processors, such as the Ryzen 7 5800X3D, where they're called 3D Vertical Cache (3D V-cache); as well as its Radeon RX 6000 discrete GPUs, where they're called Infinity Cache. The only known difference between the two is that the latter is fully on-die, while the former is stacked on top of existing silicon IP. It's being reported now, that "Phoenix" will indeed feature a stacked 3D V-cache.The exact function of this isn't known—whether it serves as a last-level cache for the CPU or iGPU. AMD's APU architecture differs from Intel's processors that have iGPUs. On the Intel chips, the L3 cache serves as town-square for the entire SoC, with each IP block contributing an L3 cache slice that make up a functionally-contiguous cache that all IP blocks can equally address over the Ring Bus. On AMD APUs such as "Cezanne" or "Rembrandt," the L3 cache is part of the CCX (CPU cores complex), and serves exclusively as last-level cache for the CPU cores. The iGPU has its own LLC, and the Infinity Fabric interconnect is the ether binding all IP blocks on the silicon.
The obvious direction for development in future APUs could be a unification of last-level cache for the CCX and iGPU, provided the cache is large enough for the function—and this can be accomplished by stacked cache. An RDNA2 GPU with performance rivaling the RTX 3060 Laptop GPU, the Radeon RX 6650M XT, based on the "Navi 23" silicon, has 32 MB of Infinity Cache. This means, with some clever cache memory-management, an LLC size in the neighborhood of 64 MB could emerge feasible for the APU.
45 Comments on AMD Ryzen 7000 "Phoenix" APUs with RDNA3 Graphics to Rock Large 3D V-Cache
Taking 64 cores and disable 48 of them (faulty or not), just to get this monstrosity called 7373X, that's insane. It's unheard of.
That doesn't make it a bad product, but no one said it was to begin with.
I won't bother reading the Phoronix article again because it describes the increased performance through benchmarks, which is a whole different thing.
The desktop-like 12950HX is $590, but even the 15 W 1255U is $426.
ark.intel.com/content/www/us/en/ark/products/codename/147470/products-formerly-alder-lake.html#@Mobile
This is interesting, if 1536 RDNA3 SP and 64MB V-cache rumour is true, it has the potential to be up to 2.5X Rembrandt.
So higher than 60W 3060M actually for the desktop DIY iteration in an optimistic scenario.
But we are talking Q3 2023 for the DIY market, how knows by then what the competition is going to offer, for Intel mobile however the rumour is for a 2560SP 14th gen processor (latest at Q3 2023)
I'm surprised no-one has brought back cache DIMMs and populated them with eDRAM as L4 for servers or desktops.
"Cache is King"
relevant timestamp t=770s
1 - I never said it's a bad product.
2 - I never said it's has no purpose.
3 - I just said that it's a crazy idea to begin with. Benchmarks won't change that because of 1 & 2.
If this trend continues, then mainstream DDR5 will settle at 6400 MHz which is 128 GB/s at best.
I see what you're saying, but I suspect there is something we haven't factored in.
A similar situation is if I would call the 3090 Ti a monstrosity because of the high power consumption, and that causes someone explain the GPU market or how Nvidia Ampere works.
When I wrote ..a while back I felt no confusion or shock, and the same goes for today. I don't want you to feel the need to explain and repeat more info about Milan-X, as I won't be buying anything like that.
If you just want to have the last word, well, I can't stop you. I have no use for it. ;)