Thursday, May 26th 2022
AMD EPYC "Bergamo" 128-core Processor Based on Same SP5 Socket as "Genoa"
AMD is launching two distinct classes of next-generation enterprise processors, the 4th Generation EPYC "Genoa" with CPU core-counts up to 96-core/192-thread; and the new EPYC "Bergamo" with a massive 128-core/256-thread compute density. Pictures of the "Genoa" MCM are already out in the wild, revealing twelve "Zen 4" CCDs built on 5 nm, and a new-generation sIOD (I/O die) that's very likely built on 6 nm. The fiberglass substrate of "Genoa" already looks crowded with twelve chiplets, making us wonder if AMD needed a larger package for "Bergamo." Turns out, it doesn't.
In its latest Corporate presentation, AMD reiterated that "Bergamo" will be based on the same SP5 (LGA-6096) package as "Genoa." This would mean that the company either made room for more CCDs, or the CCDs themselves are larger in size. AMD states that "Bergamo" CCDs are based on the "Zen 4c" microarchitecture. Details about "Zen 4c" are scarce, but from what we gather, it is a cloud-optimized variant of "Zen 4" probably with the entire ISA of "Zen 4," and power characteristics suited for high-density cloud environments. These chiplets are built on the same TSMC N5 (5 nm EUV) process as the regular "Zen 4" CCDs.
Source:
Planet 3DNow
In its latest Corporate presentation, AMD reiterated that "Bergamo" will be based on the same SP5 (LGA-6096) package as "Genoa." This would mean that the company either made room for more CCDs, or the CCDs themselves are larger in size. AMD states that "Bergamo" CCDs are based on the "Zen 4c" microarchitecture. Details about "Zen 4c" are scarce, but from what we gather, it is a cloud-optimized variant of "Zen 4" probably with the entire ISA of "Zen 4," and power characteristics suited for high-density cloud environments. These chiplets are built on the same TSMC N5 (5 nm EUV) process as the regular "Zen 4" CCDs.
14 Comments on AMD EPYC "Bergamo" 128-core Processor Based on Same SP5 Socket as "Genoa"
Bergamo server might use 8xchiplet of this instead of 12. (For this, this is just my guest, no source)
Things running fine on P-cores might crash on e-cores.
But things running fine on Zen4 will run fine on Zen4c, just a bit slower without a larger cache.
Imagine all of those areas can be ultilize to fit double the cores and L3 cache is just added by stacking V-cache vertically.
That means a 16 core CCD within the same area......
I guess they'll cluster them in 2x2 quads - something like this, though they'll probably do it more carefully than the 90 seconds it took me to photoshop that dog's dinner.