Friday, June 10th 2022
AMD RDNA3 Offers Over 50% Perf/Watt Uplift Akin to RDNA2 vs. RDNA; RDNA4 Announced
AMD in its 2022 Financial Analyst Day presentation claimed that it will repeat the over-50% generational performance/Watt uplift feat with the upcoming RDNA3 graphics architecture. This would be a repeat of the unexpected return to the high-end and enthusiast market-segments of AMD Radeon, thanks to the 50% performance/Watt uplift of the RDNA2 graphics architecture over RDNA. The company also broadly detailed the various new specifications of RDNA3 that make this possible.
To begin with, RDNA3 debuts on the TSMC N5 (5 nm) silicon fabrication node, and will debut a chiplet-based approach that's somewhat analogous to what AMD did with its 2nd Gen EPYC "Rome" and 3rd Gen Ryzen "Matisse" processors. Chiplets packed with the GPU's main number-crunching and 3D rendering machinery will make up chiplets, while the I/O components, such as memory controllers, display controllers, media engines, etc., will sit on a separate die. Scaling up the logic dies will result in a higher segment ASIC.
AMD also stated that it has re-architected the compute unit with RDNA3 to increase its IPC. The graphics pipeline is bound to get certain major changes, too. The company is doubling down on its Infinity Cache on-die cache memory technology, with RDNA3 featuring the next-generation Infinity Cache (which probably operates at higher bandwidths).
From the looks of it, RDNA3 will be exclusively based on 5 nm, and the company announced, for the very first time, the new RDNA4 graphics architecture. It shared no details about RDNA4, except that it will be based on a more advanced node than 5 nm.
AMD RDNA3 is expected to debut in the second half of 2022, with ramp across 2023. RDNA4 is slated for some time in 2024.
To begin with, RDNA3 debuts on the TSMC N5 (5 nm) silicon fabrication node, and will debut a chiplet-based approach that's somewhat analogous to what AMD did with its 2nd Gen EPYC "Rome" and 3rd Gen Ryzen "Matisse" processors. Chiplets packed with the GPU's main number-crunching and 3D rendering machinery will make up chiplets, while the I/O components, such as memory controllers, display controllers, media engines, etc., will sit on a separate die. Scaling up the logic dies will result in a higher segment ASIC.
From the looks of it, RDNA3 will be exclusively based on 5 nm, and the company announced, for the very first time, the new RDNA4 graphics architecture. It shared no details about RDNA4, except that it will be based on a more advanced node than 5 nm.
AMD RDNA3 is expected to debut in the second half of 2022, with ramp across 2023. RDNA4 is slated for some time in 2024.
121 Comments on AMD RDNA3 Offers Over 50% Perf/Watt Uplift Akin to RDNA2 vs. RDNA; RDNA4 Announced
iirc 400W is within the range of what's been rumored by the more reliable rumor folks.
edit: also remember those rumors pertained to the 7900XT relative to the 6900XT specifically.
I'm pretty sure there will be no 2x performance increase.Yes wrong thus my question. He didn't do any math. He just said rumors claim this increase.
Of course I still think the high end GPUs will be ludicrously priced power hogs, but this is very promising for lower end variants. Hopefully they don't screw the pooch with the 7500 series this time around - if it can deliver 6600-ish performance around 75W, that would be amazing. Though of course those GPUs are likely still more than a year out.
As for the specifics of the 50% number: seeing how this was presented at an investor relations day, the risk of being sued if any of this is even marginally wrong is significant, so we can trust the numbers to be accurate - at least in one SKU. And unless that SKU is the 6500XT (which manages to have garbage efficiency compared to other RDNA2 GPUs) this is very promising.
With advanced chiplet packaging I assume it's something along the lines of regular Zen based chips.
I'd say obviously nVidia was forced to drop a tier on its cards, cut mem in half to reduce price, and likely clock them up too.
Navi 31: 1 main chiplet called GCD and 6 supplementary chiplets with Infinity Cache.
Navi 32: 1 main chiplet called GCD and 4 supplementary chiplets with Infinity Cache.
I wonder what will the die size of these chiplets be?
3DCenter.org on Twitter: "AMD Navi 33/32/31 (updated) chip data, based on rumors & assumptions As @kopite7kimi pointed out, old info from last Oct is outdated updated: - 20% less WGP - no more double GCD for N31/N32 - 6 MCD for N31 = 384 MB IF$ - 4 MCD for N32 = 256 MB IF$ https://t.co/rj2G2gi9CU https://t.co/yDqeTTdSAT" / Twitter
They didn't go into specifics obviously, but the presenter said "It allows us to scale performance aggressively without the yield and cost concerns of large monolithic silicon."
but it is a new design so I suppose AMD knows what they are doing although, it is still speculation and rumor.
It is such a pity that they shot themselves in the foot by refusing to develop multi-GPU technology.
With the Multi-GPU, I think it is coming but not this time around.
Heck, the article even says as much (even if the sentence is a bit garbled):Whether that's one processing die, two, or more is currently unknown, but regardless of that it will be MCM. And, crucially, once you're disaggregating the die, the difference between running one and several processing dice is far smaller than going from a monolithic design. Given that VRAM and PCIe are on the IOD, all chiplets will have equal access to the same data - and if IC is on the IOD as has been speculated, this will also ensure a fully coherent and very fast cache between processing chiplets, ensuring that they don't need to wait on each other for data like in ordinary mGPU setups.Non-transparent multi-GPU is and has always been a dead end, requiring far too much driver and software developer effort to make useful, and needing incredibly fast (and very power hungry) interconnects to try and overcome fundamental challenges like microstuttering. Game development is already massively complex, so putting this on developers is just not feasible. And no GPU maker has the resources to fully support this on their end either. And other than that, I don't see how anyone has "refused" to develop mGPU tech? Transparent multi-GPU in the form of MCM GPUs is coming - it's just a question of when. Everything being on the same package allows for overcoming the inherent challenges of mGPU much, much more easily. With advanced packaging methods putting the dice so close that signal latecy nears zero and interconnect power drops to near nothing, you can start moving the scheduling parts of the GPU onto an IOD and make the compute chiplets "pure" compute. This is obviously not trivial whatsoever, but it's the direction things are moving in. It might take a couple of generations, but we're already seeing it in CDNA (which doesn't do real time graphics and thus has slightly fewer issues with keeping everything in sync).