Monday, September 12th 2022
NVIDIA's Third Largest Ada GPU, the AD106, Features PCIe x8 Interface
It looks like NVIDIA is finally taking AMD's route in the mid-range by giving the third-largest silicon in its next-generation GeForce "Ada" RTX 40-series a narrower PCI-Express host interface. The AD106 silicon will be NVIDIA's third largest client GPU based on the "Ada" architecture, and succeeds the GA106 powering the likes of the GeForce RTX 3060. This chip reportedly features a narrower PCI-Express x8 host interface. At this point we don't know if the AD106 comes with PCI-Express Gen 5 or Gen 4. Regardless, having a PCIe lane count of 8 could possibly impact performance of the GPU on systems with PCI-Express Gen 3, such as 10th Gen Intel "Comet Lake," or even AMD's Ryzen 7 5700G APU.
Interestingly, the same leak also claims that the AD107, the fourth largest silicon powering lower mid-range SKUs, and which succeeds the GA107, features the same PCIe lane-count of x8. This is unlike AMD, which gives the "Navi 24" silicon a PCI-Express 4.0 x4 interface. Lowering the PCIe lane count simplifies PCB design, since there are fewer PCIe lanes to be wired out in precise trace-lengths to avoid asynchrony. It also reduces the pin-count of the GPU package. NVIDIA's calculation here is that there are now at least two generations of Intel and AMD platforms with PCIe Gen 4 or later (Intel "Rocket Lake" and "Alder Lake," AMD "Zen 2," and "Zen 3,") and so it makes sense to lower the PCIe lane-count.
Source:
kopite7kimi (Twitter)
Interestingly, the same leak also claims that the AD107, the fourth largest silicon powering lower mid-range SKUs, and which succeeds the GA107, features the same PCIe lane-count of x8. This is unlike AMD, which gives the "Navi 24" silicon a PCI-Express 4.0 x4 interface. Lowering the PCIe lane count simplifies PCB design, since there are fewer PCIe lanes to be wired out in precise trace-lengths to avoid asynchrony. It also reduces the pin-count of the GPU package. NVIDIA's calculation here is that there are now at least two generations of Intel and AMD platforms with PCIe Gen 4 or later (Intel "Rocket Lake" and "Alder Lake," AMD "Zen 2," and "Zen 3,") and so it makes sense to lower the PCIe lane-count.
40 Comments on NVIDIA's Third Largest Ada GPU, the AD106, Features PCIe x8 Interface
AD103
AD104
AD106
AD107
Third largest would be AD104, AD106 at 203mm2 is one third of 4090, but sadly only one quarter of the CUDA cores 4608 or even less, 3840. Still considering how late into the cycle 3050 was released, why are they even talking about AD106 so soon. 4050 is at least a 3060/ 3060 Ti if true.
:)
cant imagine why the falloff for the 4050 would be any higher, while the 4060 may be around 5% slower? At least they aren't castrating the Ad107 GPU like AMD continues to do with RX 7500!
www.oreilly.com/library/view/pci-express-system/0321156307/0321156307_ch02lev1sec8.html
www.manualslib.com/manual/1183617/Idt-89hpes64h16g2.html?page=225&term=x12&selected=9#manual
arstechnica.com/features/2004/07/pcie/5/
knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019OddSAE
I can't access the original source of PCI-SIG documents but here is another source for PCIe 2.0 base specification, and it mentions x12:
www.cl.cam.ac.uk/~djm202/pdf/specifications/pcie/PCI_Express_Base_Rev_2.0_20Dec06a.pdf
What version of documentation were you looking at, perhaps the 6.0 spec leaves out x12 and introduces x24?
Edit: Surprise, you can buy PCIe 5.0 x24 connectors from Amphenol, they have 230 pins and would hang over the edge on a mini-ITX motherboard:
cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/ssio/ssio_cooledge_1_00mm.pdf
Does anyone know where these are used?
Boards will waste lanes, but nvidia still gets the space savings on die from a smaller pcie phy.