ChaitanyaSo not much improvements to memory both in terms of capacity and speed to be expected.

evernessinceAfter the latest AGESA update AMD CPUs can already run DDR5 8000 more reliably than Intel. The limiting factor is that you can't run those speeds 1:1, so bandwidth goes up but latency ends up being about the same. It's possible that AMD ups memory performance by keeping the same IO die while the infinity fabric speed the CPU can handle. Who knows though, this is all speculation. I do expect there to be small improvements to the IO die just due to maturity as well.

SteevoHonestly AMD seems to have figured out memory, and their next best move is cache latency for improved IPC more cores are worthless if you can't keep them busy. I would also wager they will move the IO die to a smaller node and the chiplets to a smaller node, its what they have been doing with success. I have swapped between 6000-8000 speeds and around 65ns is all she will suffer.

AnotherReaderThe cache latencies are already excellent. The core is a much smaller core than Golden Cove and still keeps up. Making the out-of-order structures bigger would be the logical next step for increased IPC. We'll see what knobs the turn in Zen 5.

SteevoMy bad, I was thinking they were still 20% behind.

ChaitanyaSo not much improvements to memory both in terms of capacity and speed to be expected.

ChippendaleFor now cpu idle of amd is way to high for my liking

ChaitanyaSo not much improvements to memory both in terms of capacity and speed to be expected.

DRAM Bandwidth

Zen 4 also moves over to DDR5, which dramatically increases the memory subsystem’s theoretical bandwidth. We saw just above 50 GB/s of read bandwidth using a 5950X equipped with DDR4-3600, or just above 88% of theoretical DRAM bandwidth. Our DDR5-6000 equipped 7950X platform achieved 72.85 GB/s at the same 3 GB test size. On one hand, that’s a notable 43% increase in memory bandwidth. On the other, Zen 4 actually sees a decrease in memory bandwidth efficiency. A 128-bit DDR5-6000 bus can theoretically reach 96 GB/s, and we only achieved 76% of that.

One theory is that Zen 4’s DRAM bandwidth is limited by the link between the memory controller and fabric. AMD’s diagram shows that the link is 32 bytes per cycle wide in both directions.


However, that is unlikely. FCLK in our testing was set to 2000 MHz. 32 bytes per cycle at 2000 MHz works out to 64 GB/s, which is well under what we were able to achieve. UCLK runs at 3000 MHz, or half of DDR transfer rate. 32 bytes per cycle at 3000 MHz should mean that full DDR bandwidth can be achieved in either direction. That does not rule out a bandwidth limitation at the link between Infinity Fabric and the memory controller, but it does suggest the link to fabric is wider than AMD’s diagram suggests.

Another related theory is that bandwidth can be improved if we mix reads and writes in a 1:1 ratio, since the link can deliver 32 bytes in each direction. However, mixing reads and writes introduces a different problem at the DRAM level. Unlike links to cache, the DRAM bus is not bidirectional and has to be explicitly switched between read and write modes. These switches are not free and force the memory bus to idle for a number of cycles, reducing achieved bandwidth. Therefore, we don’t see a significant bandwidth increase when using an access pattern that mixes reads and writes.

AusWolfConsidering that RDNA 3 doesn't offer any significant IPC uplift over RDNA 2, this news probably won't shock anyone.

AusWolfConsidering that RDNA 3 doesn't offer any significant IPC uplift over RDNA 2, this news probably won't shock anyone.

SteevoWhat does CPU have to do with GPU? This is about a CPU with a supposed 20%IPC uplift (with who knows what security issues they learned from the blue guys) over the 7000 series using the same IO die.

JismIt's something completely new and they are the first to actually implement CCD's and IO dies onto a GPU. Give it a few generations and it will be massive.

evernessinceAMD is more efficient at idle:

evernessinceAMD is more efficient at idle:

AusWolfI wonder how they got those numbers. The CPU only power on any chiplet Ryzen with EXPO/XMP enabled is in the low to mid 20s (W) at idle. Every single modern Intel CPU eats way less than that, as far as I know.

AssimilatorSo just a refresh, huh.

evernessinceAMD is more efficient at idle:

M440is it the same core design?



IMO no and this graphic is wrong.

I would say right now ryzen 7000 is 15 watt higher power consumption at idle. Something like ~50watt vs ~65watt (including dedicated gpu).

Its tolerable because a) i don't use pc for it to idle and at work it's the most efficient b) amd have very efficient mobile chips and 5000g chips so i expect improvement here c) it's a desktop pc.

AusWolfI wonder how they got those numbers. The CPU only power on any chiplet Ryzen with EXPO/XMP enabled is in the low to mid 20s (W) at idle. Every single modern Intel CPU eats way less than that, as far as I know.

M440IMO no and this graphic is wrong.

I would say right now ryzen 7000 is 15 watt higher power consumption at idle. Something like ~50watt vs ~65watt (including dedicated gpu).

Its tolerable because a) i don't use pc for it to idle and at work it's the most efficient b) amd have very efficient mobile chips and 5000g chips so i expect improvement here c) it's a desktop pc.

evernessinceIdle power consumption varies based on the memory configuration on both Intel and AMD platforms. Hence why you see some variance:





And I assume you think the above provided graph is incorrect as well? What evidence do you have that would disprove the results of multiple professional reviews?

fevgatosThe above graph is using high performance power plan. In which case yes, Intel draws around 18 to 20w. Balanced power plan drops that to below 3. Amd sadly doesn't drop any further cause of the IO die. If you had the cpus in question, you would know.