AMD earlier this week released basic enablement for the GNU Compiler Collections (GCC), which extend "Zen 4" microarchitecture awareness. The "basic enablement patch" for the new Zenver4 target is essentially similar to Zenver3, but with added support for the new AVX-512 instructions, namely AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, AVX512BITALG, and AVX512VPOPCNTDQ. Besides AVX-512, "Zen 4" is largely identical to its predecessor, architecturally, and so the enablement is rather basic. This should come just in time for software vendors to prepare for next-generation EPYC "Genoa" server processors, or even small/medium businesses building servers with Ryzen 7000-series processors.

OneRaichu, who has access to engineering samples of both the AMD "Raphael" Ryzen 7000-series, and Intel 13th Gen Core "Raptor Lake," performed IPC comparisons between the two, by disabling E-cores on the "Raptor Lake," fixing the clock speeds of both chips to 3.60 GHz, and testing them across a variety of DDR5 memory configurations. The IPC testing was done with SPEC, a mostly enterprise-relevant benchmark, but one that could prove useful in tracing where the moderately-clocked enterprise processors such as EPYC "Genoa" and Xeon Scalable "Sapphire Rapids" land in the performance charts. OneRaichu also threw in scores obtained from a 12th Gen Core "Alder Lake" processor for this reason, as its "Golden Cove" P-core powers "Sapphire Rapids" (albeit with more L2 cache).

With DDR5-4800 memory, and testing on SPECCPU2017 Rate 1, at 3.60 GHz, the AMD "Zen 4" core ends up with the highest scores in SPECint, topping even the "Raptor Cove" P-core. It scores 6.66, compared to 6.63 total of the "Raptor Cove," and 6.52 of the "Golden Cove." In the SPECfp tests, however, the "Zen 4" core falls beind "Raptor Cove." Here, scores a 9.99 total compared to 9.91 of the "Golden Cove," and 10.21 of the "Raptor Cove." Things get interesting at DDR5-6000, a frequency AMD considers its "sweetspot," The 13th Gen "Raptor Cove" P-core tops SPECint at 6.81, compared to 6.77 of the "Zen 4," and 6.71 of "Golden Cove." SPECfp sees the "Zen 4" fall behind even the "Golden Cove" at 10.04, compared to 10.20 of the "Golden Cove," and 10.46 of "Raptor Cove."

With its recent announcement of the Ryzen 7000 desktop processors, the action now shifts to the server, with AMD preparing a wide launch of its EPYC "Genoa" and "Bergamo" processors this year. Powered by the "Zen 4" microarchitecture, and contemporary I/O that includes PCI-Express Gen 5, CXL, and DDR5, these processors dial the CPU core-counts per socket up to 96 in case of "Genoa," and up to 128 in case of "Bergamo." The EPYC "Genoa" series represents the main trunk of the company's server processor lineup, with various internal configurations targeting specific use-cases.

The 96 cores are spread twelve 5 nm 8-core CCDs, each with a high-bandwidth Infinity Fabric path to the sIOD (server I/O die), which is very likely built on the 6 nm node. Lower core-count models can be built either by lowering the CCD count (ensuring more cores/CCD), or by reducing the number of cores/CCD and keeping the CCD-count constant, to yield more bandwidth/core. The leaked product-stack table below shows several of these sub-classes of "Genoa" and "Bergamo," classified by use-cases. The leaked slide also details the nomenclature AMD is using with its new processors. The leaked roadmap also mentions the upcoming "Genoa-X" processor for HPC and cloud-compute uses, which features the 3D Vertical Cache technology.

AMD in its Ryzen 7000 series launch event shared its near-future CPU architecture roadmap, in which it confirmed that the "Zen 4" microarchitecture, currently on the 5 nm foundry node, will see an optical-shrink to the 4 nm process in the near future. This doesn't necessarily indicate a new-generation CCD (CPU complex die) on 4 nm, it could even be a monolithic mobile SoC on 4 nm, or perhaps even "Zen 4c" (high core-count, low clock-speed, for cloud-compute); but it doesn't rule out the possibility of a 4 nm CCD that the company can use across both its enterprise and client processors.

The last time AMD hyphenated two foundry nodes for a single generation of the "Zen" architecture, was with the original (first-generation) "Zen," which debuted on the 14 nm node, but was optically shrunk and refined on the 12 nm node, with the company designating the evolution as "Zen+." The Ryzen 7000-series desktop processors, as well as the upcoming EPYC "Genoa" server processors, will ship with 5 nm CCDs, with AMD ticking it off in its roadmap. Chronologically placed next to it are "Zen 4" with 3D Vertical Cache (3DV Cache), and the "Zen 4c." The company is planning "Zen 4" with 3DV Cache both for its server- and desktop segments. Further down the roadmap, as we approach 2024, we see the company debut the future "Zen 5" architecture on the same 4 nm node, evolving into 3 nm on certain variants.

AMD is allegedly ready with a working "Zen 4" chiplet that has stacked 3D Vertical Cache (3DV cache) memory, which supplements the on-die L3 cache, and is found to massively improve gaming performance. "Moore's Law is Dead" reports that the Zen 4 + 3DV Cache chiplet will be used with various Ryzen 7000X3D SKUs, as well as special EPYC "Genoa" SKUs.

The 3DV Cache deployed with the "Zen 4" chiplet is a second-generation to the one on the "Zen 3 + 3DV cache" chiplet, and AMD has worked on a number of bandwidth and latency improvements, so it performs in-sync with the generationally-faster on-die L3 cache of the "Zen 4" chiplet. Unlike the CCD below it that's built on TSMC N5 (5 nm EUV), the L3D (the stacked die with the 3DV cache) is possibly be built on an older node, such as N6 (6 nm), since it only contains a slab of memory and doesn't warrant N5. "Moore's Law is Dead" reports that AMD expects to repeat the magic of the 5800X3D when it comes to gaming performance, and expects Ryzen 7000X3D processors to dominate Intel's 13th Gen "Raptor Lake" processors. This was echoed by another reliable source, greymon55.

AMD is now TSMC's second largest customer for its 5 nanometer N5 silicon fabrication node, according to a DigiTimes report. The Taiwan-based semiconductor industry observer also reports that AMD is more resilient than Intel in facing any downturns in the PC industry, in the coming few months. PC sales are expected to slump by as much as 15 percent in the near future, but the lower market-share compared to Intel; and the flexibility for AMD to move its CPU chips over to enterprise product to feed the growth in server processor segment, means that the company can ride over a bumpy road in the near future. The lower market-share translates to "lesser pain" from a slump compared to Intel. The report also says that embracing TSMC for processors "just in time" means that AMD has a front-row seat with product performance, time-to-market, yields, and delivery.

AMD is on the anvil of two major product launches on 5 nm, the Ryzen 7000 series "Raphael" desktop processors on August 30 (according to the report), and EPYC "Genoa" server processors in November 2022. The company is planning to refresh its notebook processor lineup in the first half of 2023, with "Dragon Range," and "Phoenix Point" targeting distinct market segments among notebooks. "Dragon Range" is essentially "Raphael" (5 nm chiplet + 6 nm cIOD) on a mobile-optimized BGA package, letting AMD cram up to 16 "Zen 4" cores, and take on Intel's high core-count mobile processors. The iGPU of "Dragon Range" will be basic, since designs based on this chip are expected to use discrete GPUs. "Phoenix Point" is a purpose-built mobile processor with up to 8 "Zen 4" cores, and a powerful iGPU based the RDNA3 architecture.

AMD in its Q2-2022 financial results call with analysts, confirmed that the company's next-generation Ryzen 7000 desktop processors based on the "Zen 4" microarchitecture will debut this quarter (i.e. Q3-2022, or before October 2022). CEO Dr Lisa Su stated "Looking ahead, we're on track to launch our all-new 5 nm Ryzen 7000 desktop processors and AM5 platforms later this quarter with leadership performance in gaming and content creation."

The company also stated that its next-generation Radeon 7000 series GPUs based on the RDNA3 graphics architecture are on-track for launch "later this year," without specifying whether it meant this quarter, which could mean launch any time before January 2023. AMD is also on course to beating Intel to the next-generation of server processors with DDR5 and PCIe Gen 5 support, with its EPYC "Genoa" 96-core processor slated for later this year, as Intel struggles with a Q1-2023 general availability timeline for its Xeon Scalable "Sapphire Rapids" processor.

AMD in its recent interview with TechPowerUp had asserted that 3D Vertical Cache (or 3DV Cache), isn't a one-off technology and that it would be a continual part of its roadmap. In its 2022 Financial Analyst Day presentation, the company confirmed this, by announcing variants of its CPU chiplets that have 3DV Cache, extending to both the upcoming "Zen 4" microarchitecture, and the upcoming "Zen 5," which it unveiled today.

EPYC "Genoa" is codename for the upcoming line of server processors based on the "Zen 4" CPU microarchitecture, with CPU core-counts of up to 96-core/192-thread. These feature the standard "Zen 4" CCD. The company hasn't yet announced the last-level cache (L3 cache) size of the standard "Zen 4" CCD. The company will launch the EPYC "Genoa-X" processor, which much like the EPYC "Milan-X," will incorporate 3DV Cache, with a stacked L3 cache die on top of the chiplet. "Genoa-X" is slated for a 2023 debut.

AMD's first desktop processor with DDR5 memory support, the Ryzen 7000 series "Raphael," based on the "Zen 4" microarchitecture, will come with a design focus on DDR5 memory overclocking capabilities, with the company claiming that the processors will be capable of handling DDR5 memory clock speeds "you maybe thought couldn't be possible," according to Joseph Tao who is a Memory Enabling Manager at AMD.

Tao stated: "Our first DDR5 platform for gaming is our Raphael platform and one of the awesome things about Raphael is that we are really gonna try to make a big splash with overclocking and I'll just kinda leave it there but speeds that you maybe thought couldn't be possible, may be possible with this overclocking spec." We are hearing reports of AMD innovating a new overclocking standard for DDR5 memory, which it calls RAMP (Ryzen Accelerated Memory Profile), which it is positioning as a competing standard to Intel's XMP 3.0 spec.

Here is the first picture of a next-generation AMD EPYC "Genoa" processor with its integrated heatspreader (IHS) removed. This is also possibly the first picture of a "Zen 4" CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. The "Zen 4" CCDs, built on the TSMC N5 (5 nm EUV) process, look visibly similar in size to the "Zen 3" CCDs built on the N7 (7 nm) process, which means the CCD's transistor count could be significantly higher, given the transistor-density gained from the 5 nm node. Besides more number-crunching machinery on the CPU core, we're hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the "Zen" microarchitecture.

Each "Zen 4" CCD is reported to be about 8 mm² smaller in die-area than the "Zen 3" CCD, or about 10% smaller. What's interesting, though, is that the sIOD (server I/O die) is smaller in size, too, estimated to measure 397 mm², compared to the 416 mm² of the "Rome" and "Milan" sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 nm), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 nm). Supporting this theory is the fact that the "Genoa" sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Infinity Fabric over package) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 nm, for the sIOD. AMD is expected to debut the EPYC "Genoa" enterprise processors in the second half of 2022.

Here's the first picture of AMD Socket SP5, the huge new CPU socket the company is building its next-generation EPYC "Genoa" enterprise processors around. "Genoa" will be AMD's first server products to implement the new "Zen 4" CPU cores, and next-gen I/O, including DDR5 memory and PCI-Express Gen 5. SP5, much like its predecessor SP3, is a land-grid array (LGA) socket, and has 6,096 pins.

The vast pin-count enables power to support CPU core-counts of up to 96 on the EPYC "Genoa," and up to 128 on the EPYC "Bergamo" cloud processor; a 12-channel DDR5 memory interface (24 sub-channels); and up to 128 PCI-Express 5.0 lanes. The socket's retention mechanism and processor installation procedure appears similar to that of the SP3, although the thermal requirements of SP5 will be entirely new, with processors expected to ship with TDP as high as 400 W, compared to 280 W on the current-generation EPYC "Milan." AMD is expected to debut EPYC "Genoa" in the second half of 2022.

As unreliable as Geekbench can be as a comparative benchmark, it's also an excellent source for upcoming hardware leaks and in this case more details about AMD's upcoming Zen 4 based Genoa server and workstation processors has leaked. Someone with access to a 32-core engineering sample thought it was a good idea to run geekbench on it and upload the results. As the engineering sample CPU is locked at 1.2 GHz, the actual benchmark numbers aren't particularly interesting, but the one interesting titbit we get is that AMD has increased the L2 cache to 1 MB per core, or twice as much as its predecessor.

What seems to be missing from this engineering sample is any kind of 3D V-Cache, as it only has a total of 128 MB L3 cache. Despite the gimped clock speed, the Genoa CPU is close to an EPYC 7513 in the single core tests and that CPU has a 2.6 GHz base clock and a 3.65 GHz boost clock, both system running Ubuntu 20.04 LTS. It manages to beat it in a couple of the sub-tests, such as Navigation, SQLite, HTML5, gaussian blur and face detection and it's within a few points in things like speech recognition and rigid body physics. This is quite impressive considering the Genoa engineering sample is operating at less than half the clock speed, or possibly even at a third of the clock speed of the EPYC 7513. AMD is said to be launching its Zen 4 based Genoa CPUs later this year and models with up to 96 core and 192 threads, with 12-channel DDR5 memory and PCIe 5.0 support are expected.

It will be an unexpectedly busy March for AMD, with the company launching three distinct products across its processor lines. The first one, which we reported earlier this morning, speaks of a late-March availability of the Ryzen 7 5800X3D 8-core/16-thread Socket AM4 processor, which AMD claims offers gaming performance on par with the Core i9-12900K "Alder Lake." It turns out, there are two more surprises.

Apparently the company is ready with Ryzen Threadripper PRO 5000 series workstation processors. Designed for Socket sWRX8 motherboards based on the only chipset option available—the AMD WRX80, these are the first Threadripper products based on the "Zen 3" microarchitecture, and feature 8-channel DDR4 memory, and up to 128 PCI-Express Gen4 lanes for workstation connectivity. Unfortunately, you can't buy one of these in the retail channel, as AMD is making them OEM-only. The first pre-built workstations will arrive as early as next week (March 8). At this point we still don't know if these chips use the newer "Zen 3" CCD with 3D Vertical Cache, or the conventional "Zen 3" CCD with 32 MB planar L3 cache.

Here are some of the first real-world pictures of the next-generation AMD EPYC "Genoa" enterprise processors in the Socket SP5 package. The coaster-sized 6,080-pin SP5 package gives AMD's chip-designers fiberglass substrate real-estate to dial up CCD counts up to 12, resulting in up to 96 "Zen 4" CPU cores for "Genoa." Pictured below is a 16-core prototype with just two CCDs in place, as revealed by an X-ray shot. Socket SP5 gives "Genoa" some stellar I/O capabilities, including 24x 40-bit DDR5 channels (12-channel in the classical definition), and 128x PCI-Express Gen 5.0 lanes. AMD is expected to time its EPYC "Genoa" processor launch within 2022, to best compete with Intel's Xeon "Sapphire Rapids" processor launch. It will also launch a variant codenamed "Bergamo," based on "Zen 4c" CPU cores, with up to 128 cores to go around.

The new normal ushered in by the pandemic will not only become the driving force of digital transformation but will also continue to drive the server market in 2022, according to TrendForce's investigations. It is worth noting that potential unmet demand in 2021 and the risk of future server component shortages will become medium and long-term variables that influence the market. Analyzing the shipment volume of completed servers, a growth rate of approximately 4-5% in completed server shipments is expected next year with primary shipment dynamics remaining concentrated in North American data centers with an annual growth rate of approximately 13-14%. From the supply chain perspective, the ODM Direct business model has gradually replaced the business model of the traditional server market, giving cloud service providers the ability to respond quickly to market changes. However, based on the unpredictability of the market, TrendForce assumes two forecasts for server growth trends. One, the supply situation of key components is effectively improved. Two, the supply situation of key components is exacerbated.

Just yesterday, thanks to the Linux driver update, we found information stating that AMD's upcoming EPYC Genoa processor generation based on Zen 4 core IP will have a 12-channel memory controller. However, we didn't know how AMD engineered the memory controller of this processor generation and some of its maximum capabilities. However, there is an exciting discovery. According to the report from ComputerBase, with information exclusive to them, AMD will enable up to 12 TB of DDR5 memory spread across 12 memory channels. The processor supports DDR5-5200 memory, but when all 24 memory slots (two per channel) are populated, the DDR5 maximum speed drops to 4000 MT/s.

It is unclear why this is the case, and if any difficulties were designing the controller, so the maximum speed drops when every slot is used. One reassuring thing is that the bandwidth created by 12 memory channels should be sufficient to make up for the lost speed of DDR5 memory reduction.

AMD later this month is preparing to address investors as part of a yet-unknown event. The company typically hosts Financial Analyst Day events around Q1-Q2, and goes to the investors with substantial material on the current state of the organization, the products on offer, what's on the horizon, and how it could impact the company's financials. An alleged presentation related to the November 2021 event was leaked to the web. The presentation provides a guided tour of the entire product portfolio of the company, spanning server processors, compute accelerators, consumer graphics, some client processors, and the semi-custom business.

The presentation outlines that the company has so far successfully executed its roadmaps for the client-CPU, server-CPU, graphics, and compute-accelerator segments. In the client CPU segment, it shows a successful execution up to 2021 with the "Zen 3" microarchitecture. In the server space, it mentions successful execution for its EPYC processors up to "Zen 3" with its "Milan" processors, and confirms that its next-generation "Zen 4" microarchitecture, and its sister-architecture, the "Zen 4c," will be built on the 5 nm silicon fabrication node (likely TSMC N5). The presentation also details the recently announced "Milan-X" processor for existing SP3 platforms, which debuts the 3D Vertical Cache technology, bringing up to 96 MB of L3 cache per CCD, and up to 768 MB of L3 cache (804 MB L1+L2+L3 cache) per socket.Update 10:54 UTC: The presentation can now be found on the AMD Investor Relations website.

AMD on Monday made several major announcements covering different parts of its enterprise product roadmap. These included the 3rd Gen EPYC "Milan-X" processors with 3D Vertical Cache memory; Instinct MI200 CDNA2 compute accelerators, and announcements related to next-generation "Zen 4" based EPYC "Genoa" and "Bergamo" processors that come with core counts as high as 128. The company's stock rallied up to 12%, closing up 10%, which left many in the tech community scratching their heads. It turns out that the AMD-Meta deal has a profound impact on investors.

Meta, the holding company of Facebook covering all its businesses, aspires to be a major cloud solutions provider on par with Microsoft Azure, AWS, and Google Cloud. The deal could see Meta buying large stocks of AMD processors and compute accelerators to drive its next-gen server infrastructure. Sales of enterprise processors doubled year-over-year for AMD, and EPYC processors now account for 20% of the company's revenues.

While the server industry transitions to the latest generation of processors based on the x86 platform, the Intel Ice Lake and AMD Milan CPUs entered mass production earlier this year and were shipped to certain customers, such as North American CSPs and telecommunication companies, at a low volume in 1Q21, according to TrendForce's latest investigations. These processors are expected to begin seeing widespread adoption in the server market in 3Q21. TrendForce believes that Ice Lake represents a step-up in computing performance from the previous generation due to its higher scalability and support for more memory channels. On the other hand, the new normal that emerged in the post-pandemic era is expected to drive clients in the server sector to partially migrate to the Ice Lake platform, whose share in the server market is expected to surpass 30% in 4Q21.

The ramp-up of the Intel Ice Lake and AMD Milan processors is expected to not only propel growths in server shipment for two consecutive quarters from 2Q21 to 3Q21, but also drive up the share of high-density products in North American hyperscalers' enterprise SSD purchases, according to TrendForce's latest investigations. In China, procurement activities by domestic hyperscalers Alibaba and ByteDance are expected to increase on a quarterly basis as well. With the labor force gradually returning to physical offices, enterprises are now placing an increasing number of IT equipment orders, including servers, compared to 1H21. Hence, global enterprise SSD procurement capacity is expected to increase by 7% QoQ in 3Q21. Ongoing shortages in foundry capacities, however, have led to the supply of SSD components lagging behind demand. At the same time, enterprise SSD suppliers are aggressively raising the share of large-density products in their offerings in an attempt to optimize their product lines' profitability. Taking account of these factors, TrendForce expects contract prices of enterprise SSDs to undergo a staggering 15% QoQ increase for 3Q21.

AMD in a filing with the U.S. Securities and Exchange Commission (SEC), revealed that its wafer supply agreement with GlobalFoundries has been amended. Under the new terms, AMD places orders for wafers from GlobalFoundries up to 2024, with purchase targets set for each year leading up to 2024. Beyond meeting these targets, AMD is free from all other exclusivity commitments. The agreement was previously amended in January 2019, setting annual purchase targets for 2019, 2020, and 2021, while beginning a de-coupling between AMD and GlobalFoundries. This enabled the company to source 7 nm (or smaller) chips, such as CCDs and GPUs, from other foundries, such as TSMC, while keeping GlobalFoundries exclusive for 12 nm (or larger) nodes.

The updated wafer supply agreement unlocks many possibilities for AMD. For starters, it can finally build a next-generation sIOD (server I/O die) on a more efficient node than GlobalFoundries 12LP, such as TSMC 7 nm. This transition to 7 nm will be needed as the next-gen "Genoa" EPYC processor could feature future I/O standards such as DDR5 memory and PCI-Express Gen 5, and the switching fabric for these could be too power-hungry on 12 nm. The "Zen 4" CPU core complex dies (CCDs) of "Genoa" are expected to be built on TSMC 5 nm.

The next-generation "Zen 4" CPU microarchitecture powering AMD's 4th Gen EPYC "Genoa" enterprise processors, will support 512-bit AVX instruction sets, according to an alleged company slide leaked to the web on the ChipHell forums. The slide references "AVX3-512" support in addition to BFloat16 and "other ISA extensions." This would make "Zen 4" the first AMD microarchitecture to support AVX-512. It remains to be seen which specific instructions the architecture supports, and whether all of them are available to both the enterprise and client implementations of "Zen 4," or whether AMD would take an approach similar to Intel, in only enabling certain "relevant" instructions on the client parts. The slide also mentions core counts being "greater than 64" corresponding withour story from earlier today.

AMD's next-generation EPYC enterprise processor that succeeds the upcoming 3rd Gen EYPIC "Milan," codenamed "Genoa," is expected to be the first major platform update for AMD's enterprise platforms since the 2017 debut of the "Zen" based "Naples." Implementing the latest I/O interfaces, such as DDR5 memory and PCI-Express gen 5.0, the chip will also increase CPU core counts by 50% over "Milan," according to ExecutableFix on Twitter, a reliable source with rumors from the semiconductor industry. To enable the goals of new I/O and increased core counts, AMD will transition to a new CPU socket type, the SP5. This is a 6,096-pin land grid array (LGA), and the "Genoa" MCM package on SP5 is imagined to be visibly larger than SP3-generation packages.

With the added fiberglass substrate real-estate, AMD is expected to add more CPU chiplets to the package, and ExecutableFix expects the chiplet count to be increased to 12. AMD is expected to debut the "Zen 4" microarchitecture in the enterprise space with "Genoa," with the CPU chiplets expected to be built on the 5 nm EUV silicon fabrication node. Assuming the chiplets still only pack 8 cores a piece, "Genoa" could cram up to 96 cores per socket, or up to 192 logical processors, with SMT enabled.

While AMD has only released a few Zen 3 processors which are still extremely hard to purchase for RRP we are already receiving leaks on their successors. Zen 3 Milan processors will likely be the final generation of AM4 processors before the switch to AM5. AMD appears to be preparing a bridging series of processors based on the Zen 3+ architecture before the release of Zen 4. Zen 3+ is expected to be AMD's first AM5 CPU design and should bring small IPC gains similar to the improvements from Zen to Zen+ in the range of 4% - 7%. The Zen 3+ processors will be manufactured on TSMC's refined N7 node with a potential announcement sometime later in 2021.

Zen 4 is expected to launch the next year in 2022 and will bring significant improvements potentially up to 40% over Zen 3 after clock boosts according to ChipsandChesse. A Zen 4 Genoa engineering sample reportedly performed 29% faster than an existing Zen 3 CPUs at the same clock speeds and core counts. The Zen 4 architecture will be manufactured on a 5 nm node and could potentially bring another core count increase. This would be one of the largest generational improvements for AMD since the launch of Ryzen if true. Take all this information with a heavy dose of skepticism as with any rumor.

AMD late Tuesday released its Q2-2020 financial results, which saw the company rake in revenue of $1.93 billion for the quarter, and clock a 26 percent YoY revenue growth. In both its corporate presentation targeted at the financial analysts, and its post-results conference call, AMD revealed a handful interesting bits looking into the near future. Much of the focus of AMD's presentation was in reassuring investors that [unlike Intel] it is promising a stable and predictable roadmap, that nothing has changed on its roadmap, and that it intends to execute everything on time. "Over the past couple of quarters what we've seen is that they see our performance/capability. You can count on us for a consistent roadmap. Milan point important for us, will ensure it ships later this year. Already started engaging people on Zen4/5nm. We feel customers are very open. We feel well positioned," said president and CEO Dr Lisa Su.

For starters, there was yet another confirmation from the CEO that the company will launch the "Zen 3" CPU microarchitecture across both the consumer and data-center segments before year-end, which means both Ryzen and EPYC "Milan" products based on "Zen 3." Also confirmed was the introduction of the RDNA2 graphics architecture across consumer graphics segments, and the debut of the CDNA scalar compute architecture. The company started shipping semi-custom SoCs to both Microsoft and Sony, so they could manufacture their next-generation Xbox Series X and PlayStation 5 game consoles in volumes for the Holiday shopping season. Semi-custom shipments could contribute big to the company's Q3-2020 earnings. CDNA won't play a big role in 2020 for AMD, but there will be more opportunities for the datacenter GPU lineup in 2021, according to the company. CDNA2 debuts next year.