AMD's upcoming "Zen" architecture will see a major change in the way the company designs its CPU cores. It will be a departure from the "module" core design introduced with "Bulldozer," in which two cores with shared resources constitute the indivisible unit of a multi-core processor. A "Zen" core will have dedicated resources in a way things used to be before "Bulldozer," and only the last-level cache (L3 cache), will be shared between cores. "Zen" will also implement SMT, much in the same way as Intel processors do, with HyperThreading Technology.

The first implementation of "Zen" will be an insanely powerful APU (on paper anyway), featuring 16 physical "Zen" CPU cores, 32 logical CPUs enabled with SMT, 512 KB dedicated L2 cache per core, and 32 MB of shared L3 cache. The CPU's ISA instruction set will see a spring-cleaning, with the removal of underused instruction-sets, and the introduction of new ones. Other features on this APU are equally surprising - a quad-channel DDR4 integrated memory controller, a separate HBM (high-bandwidth memory) controller dedicated to the integrated graphics, with up to 512 GB/s bandwidth, and an integrated graphics core featuring "Greenland-class" stream processors. Given that AMD is able to build 7-billion transistor GPUs on existing 28 nm processes, building an APU with these chops doesn't sound far-fetched. The company could still have to rely on a newer fab.